1 karl  1.2 //%2006////////////////////////////////////////////////////////////////////////

  2 jim.wunderlich 1.1 //
  3                    // Copyright (c) 2000, 2001, 2002 BMC Software; Hewlett-Packard Development
  4                    // Company, L.P.; IBM Corp.; The Open Group; Tivoli Systems.
  5                    // Copyright (c) 2003 BMC Software; Hewlett-Packard Development Company, L.P.;
  6                    // IBM Corp.; EMC Corporation, The Open Group.
  7                    // Copyright (c) 2004 BMC Software; Hewlett-Packard Development Company, L.P.;
  8                    // IBM Corp.; EMC Corporation; VERITAS Software Corporation; The Open Group.
  9                    // Copyright (c) 2005 Hewlett-Packard Development Company, L.P.; IBM Corp.;
 10                    // EMC Corporation; VERITAS Software Corporation; The Open Group.

 11 karl           1.2 // Copyright (c) 2006 Hewlett-Packard Development Company, L.P.; IBM Corp.;
 12                    // EMC Corporation; Symantec Corporation; The Open Group.

 13 jim.wunderlich 1.1 //
 14                    // Permission is hereby granted, free of charge, to any person obtaining a copy
 15                    // of this software and associated documentation files (the "Software"), to
 16                    // deal in the Software without restriction, including without limitation the
 17                    // rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
 18                    // sell copies of the Software, and to permit persons to whom the Software is
 19                    // furnished to do so, subject to the following conditions:

 20 karl           1.2 // 

 21 jim.wunderlich 1.1 // THE ABOVE COPYRIGHT NOTICE AND THIS PERMISSION NOTICE SHALL BE INCLUDED IN
 22                    // ALL COPIES OR SUBSTANTIAL PORTIONS OF THE SOFTWARE. THE SOFTWARE IS PROVIDED
 23                    // "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT
 24                    // LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
 25                    // PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 26                    // HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 27                    // ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 28                    // WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 29                    //
 30                    //==============================================================================
 31                    //
 32                    // Author: Mike Brasher, Inova Europe (mike-brasher@austin.rr.com)
 33                    //
 34                    //%/////////////////////////////////////////////////////////////////////////////
 35                    
 36                    #ifndef _Pegasus_Common_AtomicInt_PTHREAD_SPINLOCK_h
 37                    #define _Pegasus_Common_AtomicInt_PTHREAD_SPINLOCK_h
 38                    
 39                    #include <Pegasus/Common/Config.h>
 40                    
 41                    PEGASUS_NAMESPACE_BEGIN
 42 jim.wunderlich 1.1 
 43                    inline void AtomicIntDisableIRQs(unsigned long& flags)
 44                    {
 45                        unsigned long temp;
 46                        unsigned long x;
 47                    
 48                        asm volatile(
 49                    	"mrs %0, cpsr\n"
 50                    	"orr %1, %0, #128\n"
 51                    	"msr cpsr_c, %1\n"
 52                    	: "=r" (x), "=r" (temp)
 53                    	:
 54                    	: "memory");
 55                    
 56                        flags = x;
 57                    }
 58                    
 59                    inline void AtomicIntEnableIRQs(unsigned long x)
 60                    {
 61                        unsigned long temp;
 62                    
 63 jim.wunderlich 1.1     asm volatile(
 64                    	"mrs %0, cpsr\n"
 65                    	"orr %1, %0, #128\n"
 66                    	"msr cpsr_c, %1\n"
 67                    	: "=r" (x), "=r" (temp)
 68                    	:
 69                    	: "memory");
 70                    }
 71                    
 72                    struct AtomicType
 73                    {
 74                        volatile Uint32 n;
 75                    };
 76                    
 77                    PEGASUS_TEMPLATE_SPECIALIZATION
 78                    inline AtomicIntTemplate<AtomicType>::AtomicIntTemplate(Uint32 n)
 79                    {
 80                        _rep.n = n;
 81                    }
 82                    
 83                    PEGASUS_TEMPLATE_SPECIALIZATION
 84 jim.wunderlich 1.1 inline AtomicIntTemplate<AtomicType>::~AtomicIntTemplate()
 85                    {
 86                    }
 87                    
 88                    PEGASUS_TEMPLATE_SPECIALIZATION
 89                    inline Uint32 AtomicIntTemplate<AtomicType>::get() const
 90                    {
 91                        return _rep.n;
 92                    }
 93                    
 94                    PEGASUS_TEMPLATE_SPECIALIZATION
 95                    inline void AtomicIntTemplate<AtomicType>::set(Uint32 n)
 96                    {
 97                        _rep.n = n;
 98                    }
 99                    
100                    PEGASUS_TEMPLATE_SPECIALIZATION
101                    inline void AtomicIntTemplate<AtomicType>::inc()
102                    {
103                        unsigned long flags;
104                        AtomicIntDisableIRQs(flags);
105 jim.wunderlich 1.1     _rep.n++;
106                        AtomicIntEnableIRQs(flags);
107                    }
108                    
109                    PEGASUS_TEMPLATE_SPECIALIZATION
110                    inline void AtomicIntTemplate<AtomicType>::dec()
111                    {
112                        unsigned long flags;
113                        AtomicIntDisableIRQs(flags);
114                        _rep.n--;
115                        AtomicIntEnableIRQs(flags);
116                    }
117                    
118                    PEGASUS_TEMPLATE_SPECIALIZATION
119                    inline bool AtomicIntTemplate<AtomicType>::decAndTestIfZero()
120                    {
121                        Uint32 tmp;
122                        unsigned long flags;
123                        AtomicIntDisableIRQs(flags);
124                        tmp = --_rep.n;
125                        AtomicIntEnableIRQs(flags);
126 jim.wunderlich 1.1     return tmp == 0;
127                    }
128                    
129                    PEGASUS_NAMESPACE_END
130                    
131                    #endif /* _Pegasus_Common_AtomicInt_PTHREAD_SPINLOCK_h */