1 karl 1.1 // ===================================================================
2 // Title: Device Controller
3 // $State: Preliminary $
4 // $Date: 2004/03/19 15:28:38 $
5 // $Source: /home/dmtf2/dotorg/var/cvs/repositories/dev/Schema/MOF/Device_Controller.mof,v $
6 // $Revision: 1.2 $
7 // ===================================================================
8 //#pragma inLine ("Includes/copyright.inc")
9 // Copyright 1998-2004 Distributed Management Task Force, Inc. (DMTF).
10 // All rights reserved.
11 // DMTF is a not-for-profit association of industry members dedicated
12 // to promoting enterprise and systems management and interoperability.
13 // DMTF specifications and documents may be reproduced for uses
14 // consistent with this purpose by members and non-members,
15 // provided that correct attribution is given.
16 // As DMTF specifications may be revised from time to time,
17 // the particular version and release date should always be noted.
18 //
19 // Implementation of certain elements of this standard or proposed
20 // standard may be subject to third party patent rights, including
21 // provisional patent rights (herein "patent rights"). DMTF makes
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23 // of such rights, and is not responsible to recognize, disclose, or
24 // identify any or all such third party patent right, owners or
25 // claimants, nor for any incomplete or inaccurate identification or
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28 // legal theory whatsoever, for failure to recognize, disclose, or
29 // identify any such third party patent rights, or for such party's
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39 //
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43 karl 1.1 // http://www.dmtf.org/about/policies/disclosures.php.
44 //#pragma inLine
45 // ===================================================================
46 // Description: The Device Model extends the management concepts that
47 // are related to LogicalDevices. This file defines
48 // the concepts and classes for Controllers.
49 //
50 // The object classes below are listed in an order that
51 // avoids forward references. Required objects, defined
52 // by other working groups, are omitted.
53 // ==================================================================
54 // Change Log for v2.8 Final
55 // CR1202 - Remove Experimental Qualifier
56 // CR1233 - SysDev omnibus CR - Minor MOF corrections
57 //
58 // CR1071 - Reintroduce PortController and SCSILun.
59 // CR885 - Add Serial ATA to Controller.protocolssupported
60 // CR1015 - ProtocolController:
61 // - Change descriptions for controller,controlledby
62 // - deprecate scsicontroller,scsiinterface
63 // - remove SCSILun
64 karl 1.1 //
65 // Change Log for v2.7 Final
66 // CR934 - Remove Controller.PortNumber
67 // CR971 - Remove PortController and SCSILUN, so they can remain
68 // experimental in 2.8.
69 //
70 // Change Log for v2.7
71 // CR622 - Fix the DMI mapping string to include the attribute number
72 // for Controller.ProtocolSupported, .MaxNumberControlled, &
73 // .ProtocolDescription,
74 // SCSIController.MaxDataWidth & .MaxTransferRate,
75 // SCSIInterface.InitiatorId, .TargetId & .SCSISignal
76 // CR632 - Add PortController
77 // CR654 - Update the description for Controller
78 // - Add Controller.PortNumber
79 // - Update the Description for ControlledBy
80 // - Add ControlledBy.DeviceNumber
81 // - Add SCSILUN
82 // CR830 - Update the Description for ControlledBy
83 // - Modify type of ControlledBy.DeviceNumber from uint64 to
84 // a string
85 karl 1.1 // - Add ControlledBy.AccessMode and ControlledBy.AccessPriority
86 // - Update SCSILUN.DeviceNumber to match change to ContolledBy
87 // CR892 - Fix the subclassing inconsistency of VideoController
88 // ==================================================================
89
90 #pragma locale ("en_US")
91
92
93 // ===================================================================
94 // Controller
95 // ===================================================================
96 [Abstract, Version ( "2.8.0" ), Description (
97 "Controller is a superclass for grouping the miscellaneous "
98 "control-related Devices that provide a 'classic' bus master "
99 "interface. Examples of Controllers are USBControllers, "
100 "SerialControllers, etc. The Controller class is an abstraction "
101 "for Devices with a single protocol stack, which exist to "
102 "control communications (data, control, and reset) to "
103 "'downstream' devices. Note that a new abstract class "
104 "(ProtocolController) has been created to model more complex "
105 "interface controllers such as SCSI.")]
106 karl 1.1 class CIM_Controller : CIM_LogicalDevice {
107
108 [Description (
109 "Time of last reset of the Controller.")]
110 datetime TimeOfLastReset;
111
112 [Description (
113 "The protocol used by the Controller to access 'controlled' "
114 "Devices."),
115 ValueMap { "1", "2", "3", "4", "5", "6", "7", "8", "9", "10",
116 "11", "12", "13", "14", "15", "16", "17", "18", "19", "20",
117 "21", "22", "23", "24", "25", "26", "27", "28", "29", "30",
118 "31", "32", "33", "34", "35", "36", "37", "38", "39", "40",
119 "41", "42", "43", "44", "45", "46", "47", "48" },
120 Values { "Other", "Unknown", "EISA", "ISA", "PCI", "ATA/ATAPI",
121 "Flexible Diskette", "1496", "SCSI Parallel Interface",
122 // 10
123 "SCSI Fibre Channel Protocol", "SCSI Serial Bus Protocol",
124 "SCSI Serial Bus Protocol-2 (1394)",
125 "SCSI Serial Storage Architecture", "VESA", "PCMCIA",
126 "Universal Serial Bus", "Parallel Protocol", "ESCON",
127 karl 1.1 "Diagnostic",
128 // 20
129 "I2C", "Power", "HIPPI", "MultiBus", "VME", "IPI",
130 "IEEE-488", "RS232", "IEEE 802.3 10BASE5",
131 "IEEE 802.3 10BASE2",
132 // 30
133 "IEEE 802.3 1BASE5", "IEEE 802.3 10BROAD36",
134 "IEEE 802.3 100BASEVG", "IEEE 802.5 Token-Ring",
135 "ANSI X3T9.5 FDDI", "MCA", "ESDI", "IDE", "CMD", "ST506",
136 // 40
137 "DSSI", "QIC2", "Enhanced ATA/IDE", "AGP",
138 "TWIRP (two-way infrared)", "FIR (fast infrared)",
139 "SIR (serial infrared)", "IrBus", "Serial ATA" },
140 MappingStrings { "MIF.DMTF|Bus Port|004.2",
141 "MIF.DMTF|Disks|003.3" },
142 ModelCorrespondence { "CIM_Controller.ProtocolDescription" }]
143 uint16 ProtocolSupported;
144
145 [Description (
146 "Maximum number of directly addressable entities supported "
147 "by this Controller. A value of 0 should be used if the "
148 karl 1.1 "number is unknown or unlimited."),
149 MappingStrings { "MIF.DMTF|Bus Port|004.9" }]
150 uint32 MaxNumberControlled;
151
152 [Description (
153 "A free form string providing more information related to "
154 "the ProtocolSupported by the Controller."),
155 MappingStrings { "MIF.DMTF|Bus Port|004.3" },
156 ModelCorrespondence { "CIM_Controller.ProtocolSupported" }]
157 string ProtocolDescription;
158 };
159
160
161 // ===================================================================
162 // ControlledBy
163 // ===================================================================
164 [Association, Version ( "2.8.0" ), Description (
165 "The ControlledBy relationship indicates which Devices are "
166 "controlled by a CIM_Controller.")]
167 class CIM_ControlledBy : CIM_DeviceConnection {
168
169 karl 1.1 [Override ( "Antecedent" ), Description (
170 "The Controller.")]
171 CIM_Controller REF Antecedent;
172
173 [Override ( "Dependent" ), Description (
174 "The controlled Device.")]
175 CIM_LogicalDevice REF Dependent;
176
177 [Description (
178 "The State property indicates whether the Controller is "
179 "actively commanding or accessing the Device (value=1) or "
180 "not (value=2). Also, the value, \"Unknown\" (0), can be "
181 "defined. This information is necessary when a LogicalDevice "
182 "can be commanded by, or accessed through, multiple "
183 "Controllers."),
184 ValueMap { "0", "1", "2" },
185 Values { "Unknown", "Active", "Inactive" }]
186 uint16 AccessState;
187
188 [Description (
189 "The time that the downstream Device was last reset by the "
190 karl 1.1 "Controller.")]
191 datetime TimeOfDeviceReset;
192
193 [Description (
194 "Number of hard resets issued by the Controller. A hard "
195 "reset returns the Device to its initialization or 'boot-up' "
196 "state. All internal Device state information and data are "
197 "lost."),
198 Counter]
199 uint32 NumberOfHardResets;
200
201 [Description (
202 "Number of soft resets issued by the Controller. A soft "
203 "reset does not completely clear current Device state and/or "
204 "data. Exact semantics are dependent on the Device, and on "
205 "the protocols and mechanisms used to communicate to it."),
206 Counter]
207 uint32 NumberOfSoftResets;
208
209 [Description (
210 "Address of associated Device in context of the antecedent "
211 karl 1.1 "Controller.")]
212 string DeviceNumber;
213
214 [Description (
215 "This property describes the accessibility of the device "
216 "thru the antedecent controller."),
217 ValueMap { "2", "3", "4" },
218 Values { "ReadWrite", "ReadOnly", "NoAccess" }]
219 uint16 AccessMode;
220
221 [Description (
222 "The property describes the priority given to accesses of "
223 "the device thru this controller. The highest priority path "
224 "will have the lowest value for this parameter.")]
225 uint16 AccessPriority;
226 };
227
228
229 // ===================================================================
230 // ESCONController
231 // ===================================================================
232 karl 1.1 [Version ( "2.6.0" ), Description (
233 "Capabilities and management of an ESCONController.")]
234 class CIM_ESCONController : CIM_Controller {
235 };
236
237
238 // ===================================================================
239 // IDEController
240 // ===================================================================
241 [Version ( "2.6.0" ), Description (
242 "Capabilities and management of an IDEController.")]
243 class CIM_IDEController : CIM_Controller {
244 };
245
246
247 // ===================================================================
248 // InfraredController
249 // ===================================================================
250 [Version ( "2.6.0" ), Description (
251 "Capabilities and management of an InfraredController.")]
252 class CIM_InfraredController : CIM_Controller {
253 karl 1.1 };
254
255
256 // ===================================================================
257 // ManagementController
258 // ===================================================================
259 [Version ( "2.6.0" ), Description (
260 "Capabilities and managment of a ManagementController. An I2C "
261 "microcontroller is a type of ManagementController.")]
262 class CIM_ManagementController : CIM_Controller {
263 };
264
265
266 // ===================================================================
267 // ParallelController
268 // ===================================================================
269 [Version ( "2.6.0" ), Description (
270 "Capabilities and management of the ParallelController.")]
271 class CIM_ParallelController : CIM_Controller {
272
273 [Description (
274 karl 1.1 "Set to true if the ParallelController supports DMA."),
275 MappingStrings { "MIF.DMTF|Parallel Ports|003.7" }]
276 boolean DMASupport;
277
278 [Description (
279 "An integer enumeration indicating the capabilities of the "
280 "ParallelController."),
281 ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8" },
282 Values { "Unknown", "Other", "XT/AT Compatible",
283 "PS/2 Compatible", "ECP", "EPP", "PC-98", "PC-98-Hireso",
284 "PC-H98" },
285 MappingStrings { "MIF.DMTF|Parallel Ports|003.8" },
286 ArrayType ( "Indexed" ),
287 ModelCorrespondence {
288 "CIM_ParallelController.CapabilityDescriptions" }]
289 uint16 Capabilities[];
290
291 [Description (
292 "An array of free-form strings providing more detailed "
293 "explanations for any of the ParallelController features "
294 "indicated in the Capabilities array. Note, each entry of "
295 karl 1.1 "this array is related to the entry in the Capabilities "
296 "array that is located at the same index."),
297 ArrayType ( "Indexed" ),
298 ModelCorrespondence { "CIM_ParallelController.Capabilities" }]
299 string CapabilityDescriptions[];
300
301 [Description (
302 "An enumeration indicating the operational security for the "
303 "Controller. For example, information that the Device's "
304 "external interface is locked out (value=4) or \"Boot "
305 "Bypass\" (value=6) can be described using this property."),
306 ValueMap { "1", "2", "3", "4", "5", "6" },
307 Values { "Other", "Unknown", "None",
308 "External Interface Locked Out",
309 "External Interface Enabled", "Boot Bypass" },
310 MappingStrings { "MIF.DMTF|Parallel Ports|003.10" }]
311 uint16 Security;
312 };
313
314
315 // ===================================================================
316 karl 1.1 // PCMCIAController
317 // ===================================================================
318 [Version ( "2.6.0" ), Description (
319 "Capabilities and management of a PCMCIAController.")]
320 class CIM_PCMCIAController : CIM_Controller {
321 };
322
323
324 // ===================================================================
325 // SCSIController
326 // ===================================================================
327 [Deprecated { "CIM_SCSIProtocolController" }, Version ( "2.8.0" ),
328 Description (
329 "The use of this class is deprecated in lieu of "
330 "SCSIProtocolController. The latter reflects the protocol- "
331 "related issues of SCSI interfaces, since these are not bus "
332 "master-type Controllers. Capabilities and management of the "
333 "SCSIController.")]
334 class CIM_SCSIController : CIM_Controller {
335
336 [Deprecated { "No Value" }, Description (
337 karl 1.1 "An integer enumeration indicating whether or not the "
338 "SCSIController provides redundancy or protection against "
339 "device failures."),
340 ValueMap { "1", "2", "3", "4", "5", "6" },
341 Values { "Other", "Unknown", "Unprotected", "Protected",
342 "Protected through SCC (SCSI-3 Controller Command)",
343 "Protected through SCC-2 (SCSI-3 Controller Command)" },
344 MappingStrings { "MIF.DMTF|Storage Controller|001.3" }]
345 uint16 ProtectionManagement;
346
347 [Deprecated { "No Value" }, Description (
348 "Maximum data width (in bits) supported by the SCSI "
349 "Controller."),
350 Units ( "Bits" ),
351 MappingStrings { "MIF.DMTF|Bus Port|004.7" }]
352 uint32 MaxDataWidth;
353
354 [Deprecated { "No Value" }, Description (
355 "Maximum transfer rate (in Bits per Second) supported by the "
356 "SCSIController."),
357 Units ( "Bits per Second" ),
358 karl 1.1 MappingStrings { "MIF.DMTF|Bus Port|004.8" }]
359 uint64 MaxTransferRate;
360
361 [Deprecated { "No Value" }, Description (
362 "Number of SCSIController timeouts that have occurred since "
363 "the TimeOfLastReset."),
364 Counter]
365 uint32 ControllerTimeouts;
366
367 [Deprecated { "No Value" }, Description (
368 "Signal capabilities that can be supported by the SCSI "
369 "Controller. For example, the Controller may support "
370 "\"Single Ended\" and \"Differential\". In this case, the "
371 "values 3 and 4 would be written to the Signal Capabilities "
372 "array."),
373 ValueMap { "1", "2", "3", "4", "5", "6" },
374 Values { "Other", "Unknown", "Single Ended", "Differential",
375 "Low Voltage Differential", "Optical" },
376 ModelCorrespondence { "CIM_SCSIInterface.SCSISignal" }]
377 uint16 SignalCapabilities[];
378 };
379 karl 1.1
380 // ===================================================================
381 // SCSIInterface
382 // ===================================================================
383 [Association, Deprecated { "CIM_ProtocolControllerAccessesUnit" },
384 Version ( "2.8.0" ), Description (
385 "The use of this class is deprecated in lieu of "
386 "ProtocolControllerForUnit, since the SCSIController class "
387 "involved in this association is itself deprecated. The "
388 "protocol-related aspects of SCSI are better reflected in the "
389 "new classes and associations. SCSIInterface is a ControlledBy "
390 "relationship indicating which Devices are accessed through a "
391 "SCSIController and the characteristics of this access.")]
392 class CIM_SCSIInterface : CIM_ControlledBy {
393
394 [Deprecated { "No Value" }, Override ( "Antecedent" ),
395 Description (
396 "The SCSIController.")]
397 CIM_SCSIController REF Antecedent;
398
399 [Deprecated { "No Value" }, Description (
400 karl 1.1 "Number of SCSI timeouts that have occurred since last hard "
401 "or soft reset related to the controlled Device. The time of "
402 "last reset is indicated in the TimeOfDeviceReset property, "
403 "inherited from the ControlledBy association."),
404 Counter]
405 uint32 SCSITimeouts;
406
407 [Deprecated { "No Value" }, Description (
408 "Number of SCSI retries that have occurred since last hard "
409 "or soft reset related to the controlled Device. The time of "
410 "last reset is indicated in the TimeOfDeviceReset property, "
411 "inherited from the ControlledBy association."),
412 Counter,
413 MappingStrings { "MIF.DMTF|Mass Storage Statistics|001.18" }]
414 uint32 SCSIRetries;
415
416 [Deprecated { "No Value" }, Description (
417 "The SCSI Initiator ID."),
418 MappingStrings { "MIF.DMTF|Bus Port|004.5" }]
419 uint32 InitiatorId;
420
421 karl 1.1 [Deprecated {
422 "CIM_ProtocolControllerAccessesUnit.TargetControllerNumber" },
423 Description (
424 "The SCSI Target ID."),
425 MappingStrings { "MIF.DMTF|Bus Port|004.5" }]
426 uint32 TargetId;
427
428 [Deprecated { "CIM_ProtocolControllerForDevice.DeviceNumber" },
429 Description (
430 "The SCSI Target LUN."),
431 MappingStrings { "MIF.DMTF|Storage Devices|001.4" }]
432 uint64 TargetLUN;
433
434 [Deprecated { "No Value" }, Description (
435 "SCSIReservation indicates the type of SCSI reservation that "
436 "currently exists between the source and destination."),
437 ValueMap { "0", "1", "2", "3" },
438 Values { "Unknown", "None", "Simple", "Persistent" }]
439 uint16 SCSIReservation;
440
441 [Deprecated { "No Value" }, Description (
442 karl 1.1 "The SCSI signal characteristics being used for this "
443 "connection. The value listed here must also be listed in "
444 "the SCSIController's SignalCapabilities field."),
445 ValueMap { "1", "2", "3", "4", "5", "6" },
446 Values { "Other", "Unknown", "Single Ended", "Differential",
447 "Low Voltage Differential", "Optical" },
448 MappingStrings { "MIF.DMTF|Bus Port|004.4" },
449 ModelCorrespondence { "CIM_SCSIController.SignalCapabilities" }]
450 uint16 SCSISignal;
451
452 [Deprecated { "No Value" }, Description (
453 "Maximum number of Command Descriptor Blocks (CDBs) that can "
454 "be supported by the target. This data can not be obtained "
455 "under all circumstances.")]
456 uint32 MaxQueueDepth;
457
458 [Deprecated { "No Value" }, Description (
459 "The maximum number of concurrent Command Descriptor Blocks "
460 "(CDBs) that the initiator will send to the target. This "
461 "value should never be greater than MaxQueueDepth.")]
462 uint32 QueueDepthLimit;
463 karl 1.1 };
464
465 // ===================================================================
466 // SerialController
467 // ===================================================================
468 [Version ( "2.6.0" ), Description (
469 "Capabilities and management of the SerialController.")]
470 class CIM_SerialController : CIM_Controller {
471
472 [Description (
473 "The Capabilities property defines chip level compatibility "
474 "for the SerialController. Therefore, this property "
475 "describes the buffering and other capabilities of the "
476 "SerialController, that may be inherent in the chip "
477 "hardware. The property is an enumerated integer."),
478 ValueMap { "1", "2", "3", "4", "5", "6", "160", "161" },
479 Values { "Other", "Unknown", "XT/AT Compatible",
480 "16450 Compatible", "16550 Compatible", "16550A Compatible",
481 // 160
482 "8251 Compatible", "8251FIFO Compatible" },
483 MappingStrings { "MIF.DMTF|Serial Ports|004.7" },
484 karl 1.1 ArrayType ( "Indexed" ),
485 ModelCorrespondence {
486 "CIM_SerialController.CapabilityDescriptions" }]
487 uint16 Capabilities[];
488
489 [Description (
490 "An array of free-form strings providing more detailed "
491 "explanations for any of the SerialController features "
492 "indicated in the Capabilities array. Note, each entry of "
493 "this array is related to the entry in the Capabilities "
494 "array that is located at the same index."),
495 ArrayType ( "Indexed" ),
496 ModelCorrespondence { "CIM_SerialController.Capabilities" }]
497 string CapabilityDescriptions[];
498
499 [Description (
500 "Maximum baud rate in Bits per Second supported by the "
501 "SerialController."),
502 Units ( "Bits per Second" ),
503 MappingStrings { "MIF.DMTF|Serial Ports|004.6" }]
504 uint32 MaxBaudRate;
505 karl 1.1
506 [Description (
507 "An enumeration indicating the operational security for the "
508 "Controller. For example, information that the Device's "
509 "external interface is locked out (value=4) or \"Boot "
510 "Bypass\" (value=6) can be described using this property."),
511 ValueMap { "1", "2", "3", "4", "5", "6" },
512 Values { "Other", "Unknown", "None",
513 "External Interface Locked Out",
514 "External Interface Enabled", "Boot Bypass" },
515 MappingStrings { "MIF.DMTF|Serial Ports|004.9" }]
516 uint16 Security;
517 };
518
519
520 // ===================================================================
521 // SerialInterface
522 // ===================================================================
523 [Association, Version ( "2.6.0" ), Description (
524 "SerialInterface is a ControlledBy relationship indicating "
525 "which Devices are accessed through the SerialController and "
526 karl 1.1 "the characteristics of this access.")]
527 class CIM_SerialInterface : CIM_ControlledBy {
528
529 [Override ( "Antecedent" ), Description (
530 "The SerialController.")]
531 CIM_SerialController REF Antecedent;
532
533 [Override ( "NegotiatedDataWidth" ), Description (
534 "For the SerialInterface, NegotiatedDataWidth is the number "
535 "of data bits to be transmitted, without stop bits or "
536 "parity."),
537 Units ( "Bits" )]
538 uint32 NegotiatedDataWidth;
539
540 [Description (
541 "Number of stop bits to be transmitted."),
542 Units ( "Bits" )]
543 uint16 NumberOfStopBits;
544
545 [Description (
546 "Information on the parity setting for transmitted data. No "
547 karl 1.1 "parity (value=1), even (2) or odd (3) can be specified."),
548 ValueMap { "0", "1", "2", "3" },
549 Values { "Unknown", "None", "Even", "Odd" }]
550 uint16 ParityInfo;
551
552 [Description (
553 "An integer enumeration indicating the flow control "
554 "(Xon-Xoff and/or RTS/CTS) for transmitted data."),
555 ValueMap { "0", "1", "2", "3", "4", "5" },
556 Values { "Unknown", "Not Supported", "None", "XonXoff",
557 "RTS/CTS", "Both XonXoff and RTS/CTS" }]
558 uint16 FlowControlInfo;
559 };
560
561
562 // ===================================================================
563 // SSAController
564 // ===================================================================
565 [Version ( "2.6.0" ), Description (
566 "Capabilities and management of an SSAController (Serial "
567 "Storage Architecture).")]
568 karl 1.1 class CIM_SSAController : CIM_Controller {
569 };
570
571
572 // ===================================================================
573 // USBController
574 // ===================================================================
575 [Version ( "2.6.0" ), Description (
576 "Capabilities and managment of a USB Host Controller.")]
577 class CIM_USBController : CIM_Controller {
578
579 [Description (
580 "Indicates the latest USB Version supported by the "
581 "Controller. The property is expressed as a Binary-Coded "
582 "Decimal (BCD) where a decimal point is implied between the "
583 "2nd and 3rd digits. For example, a value of 0x201 indicates "
584 "that version 2.01 is supported.")]
585 uint16 USBVersion;
586
587 [Description (
588 "The type of interface used between the host system software "
589 karl 1.1 "and the USBController."),
590 ValueMap { "0", "1", "2", "3" },
591 Values { "Unknown", "Other", "UHCI", "OHCI" },
592 ModelCorrespondence { "CIM_USBController.ControllerVersion" }]
593 uint16 InterfaceType;
594
595 [Description (
596 "Indicates the version of the USB Host Controller register "
597 "set, specific to the InterfaceType. The property is "
598 "expressed as a Binary-Coded Decimal (BCD) value where a "
599 "decimal point is implied between the 2nd and 3rd digits. "
600 "For example, a value of 0x103 indicates that version 1.03 "
601 "is supported."),
602 ModelCorrespondence { "CIM_USBController.InterfaceType" }]
603 uint16 ControllerVersion;
604 };
605
606
607 // ===================================================================
608 // VideoController
609 // ===================================================================
610 karl 1.1 [Version ( "2.8.0" ), Description (
611 "Capabilities and management of the VideoController.")]
612 class CIM_VideoController : CIM_Controller {
613
614 [Override ( "Description" ),
615 MappingStrings { "MIF.DMTF|Video|004.18" }]
616 string Description;
617
618 [Description (
619 "A free-form string describing the video "
620 "processor/Controller.")]
621 string VideoProcessor;
622
623 [Description (
624 "An integer enumeration indicating the type of video memory."),
625 ValueMap { "1", "2", "3", "4", "5", "6", "7", "8", "9", "10",
626 "11", "12", "13" },
627 Values { "Other", "Unknown", "VRAM", "DRAM", "SRAM", "WRAM",
628 "EDO RAM", "Burst Synchronous DRAM", "Pipelined Burst SRAM",
629 //10
630 "CDRAM", "3DRAM", "SDRAM", "SGRAM" },
631 karl 1.1 MappingStrings { "MIF.DMTF|Video|004.6" }]
632 uint16 VideoMemoryType;
633
634 [Description (
635 "Number of video pages supported given the current "
636 "resolutions and available memory.")]
637 uint32 NumberOfVideoPages;
638
639 [Description (
640 "Maximum amount of memory supported in bytes."),
641 Units ( "Bytes" )]
642 uint32 MaxMemorySupported;
643
644 [Description (
645 "An array of integers indicating the graphics and 3D "
646 "capabilities of the VideoController."),
647 ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8" },
648 Values { "Unknown", "Other", "Graphics Accelerator",
649 "3D Accelerator", "PCI Fast Write", "MultiMonitor Support",
650 "PCI Mastering", "Second Monochrome Adapter Support",
651 "Large Memory Address Support" }, ArrayType ( "Indexed" ),
652 karl 1.1 ModelCorrespondence {
653 "CIM_VideoController.CapabilityDescriptions" }]
654 uint16 AcceleratorCapabilities[];
655
656 [Description (
657 "An array of free-form strings providing more detailed "
658 "explanations for any of the video Accelerator features "
659 "indicated in the Capabilities array. Note, each entry of "
660 "this array is related to the entry in the Capabilities "
661 "array that is located at the same index."),
662 ArrayType ( "Indexed" ),
663 ModelCorrespondence {
664 "CIM_VideoController.AcceleratorCapabilities" }]
665 string CapabilityDescriptions[];
666
667 [Description (
668 "The number of bits used to display each pixel."),
669 Units ( "Bits" ),
670 MappingStrings { "MIF.DMTF|Video|004.12" }]
671 uint32 CurrentBitsPerPixel;
672
673 karl 1.1 [Description (
674 "Current number of horizontal pixels."),
675 Units ( "Pixels" ),
676 MappingStrings { "MIF.DMTF|Video|004.11" }]
677 uint32 CurrentHorizontalResolution;
678
679 [Description (
680 "Current number of vertical pixels."),
681 Units ( "Pixels" ),
682 MappingStrings { "MIF.DMTF|Video|004.10" }]
683 uint32 CurrentVerticalResolution;
684
685 [Description (
686 "Maximum refresh rate of the VideoController in Hertz."),
687 Units ( "Hertz" ),
688 MappingStrings { "MIF.DMTF|Video|004.5" }]
689 uint32 MaxRefreshRate;
690
691 [Description (
692 "Minimum refresh rate of the Video Controller in Hertz."),
693 Units ( "Hertz" ),
694 karl 1.1 MappingStrings { "MIF.DMTF|Video|004.4" }]
695 uint32 MinRefreshRate;
696
697 [Description (
698 "Current refresh rate in Hertz."),
699 Units ( "Hertz" ),
700 MappingStrings { "MIF.DMTF|Video|004.15" }]
701 uint32 CurrentRefreshRate;
702
703 [Description (
704 "Current scan mode. \"Interlaced\" (value=3) or \"Non "
705 "Interlaced\" (4) can be defined using this property."),
706 ValueMap { "1", "2", "3", "4" },
707 Values { "Other", "Unknown", "Interlaced", "Non Interlaced" },
708 MappingStrings { "MIF.DMTF|Video|004.8" }]
709 uint16 CurrentScanMode;
710
711 [Description (
712 "If in character mode, number of rows for this Video "
713 "Controller. Otherwise, enter 0."),
714 MappingStrings { "MIF.DMTF|Video|004.13" }]
715 karl 1.1 uint32 CurrentNumberOfRows;
716
717 [Description (
718 "If in character mode, number of columns for this "
719 "VideoController. Otherwise, enter 0."),
720 MappingStrings { "MIF.DMTF|Video|004.14" }]
721 uint32 CurrentNumberOfColumns;
722
723 [Description (
724 "Number of colors supported at the current resolutions.")]
725 uint64 CurrentNumberOfColors;
726 };
727
728
729 // ===================================================================
730 // PCVideoController
731 // ===================================================================
732 [Version ( "2.6.0" ), Description (
733 "Capabilities and management of a PCVideoController, a subtype "
734 "of VideoController.")]
735 class CIM_PCVideoController : CIM_VideoController {
736 karl 1.1
737 [Description (
738 "The video architecture. For example, VGA (value=5) or PC-98 "
739 "(160) may be specified."),
740 ValueMap { "1", "2", "3", "4", "5", "6", "7", "8", "9", "10",
741 "11", "12", "160" },
742 Values { "Other", "Unknown", "CGA", "EGA", "VGA", "SVGA", "MDA",
743 "HGC", "MCGA",
744 // 10
745 "8514A", "XGA", "Linear Frame Buffer", "PC-98" },
746 MappingStrings { "MIF.DMTF|Video|004.2" }]
747 uint16 VideoArchitecture;
748
749 [Description (
750 "Current video mode."),
751 MappingStrings { "MIF.DMTF|Video|004.3" }]
752 uint16 VideoMode;
753
754 [Description (
755 "Current number of color planes. If this value is not "
756 "applicable for the current video configuration, enter 0.")]
757 karl 1.1 uint16 NumberOfColorPlanes;
758 };
759
760
761 // ===================================================================
762 // AGPVideoController
763 // ===================================================================
764 [Version ( "2.7.0" ), Description (
765 "Capabilities and management of an AGPVideoController.")]
766 class CIM_AGPVideoController : CIM_VideoController {
767
768 [Deprecated { "CIM_VideoController.AcceleratorCapabilities" },
769 Description (
770 "This property has been incorporated into the inherited "
771 "AcceleratorCapabilities property. Capabilities of the AGP "
772 "Graphics Controller. For example, the Device may support "
773 "multiple monitors, PCI Mastering and large memory "
774 "addresses. In this case, the values 3, 4 and 6 would be "
775 "written to the Capabilities array."),
776 ValueMap { "0", "1", "2", "3", "4", "5", "6" },
777 Values { "Unknown", "Other", "PCI Fast Write",
778 karl 1.1 "MultiMonitor Support", "PCI Mastering",
779 "Second Monochrome Adapter Support",
780 "Large Memory Address Support" }, ArrayType ( "Indexed" ),
781 ModelCorrespondence {
782 "CIM_AGPVideoController.CapabilityDescriptions" }]
783 uint16 Capabilities[];
784
785 [Description (
786 "Size of the non-local video memory in KB."),
787 Units ( "KiloBytes" )]
788 uint32 NonlocalVideoMemorySize;
789
790 [Description (
791 "Width of the internal bus in the graphics Controller, in "
792 "bits."),
793 Units ( "Bits" )]
794 uint32 LocalBusWidth;
795
796 [Description (
797 "An integer enumeration indicating the usage model of the "
798 "graphics Controller. Usage model indicates how the "
799 karl 1.1 "Controller does manipulations of graphics surfaces, "
800 "textures, etc. in memory. DMA indicates that the graphics "
801 "Controller brings structures from the system memory to its "
802 "local memory to perform needed manipulations or renderings. "
803 "Execute specifies that the graphics Controller can directly "
804 "access a specified region in main memory (called the "
805 "graphics aperture) using GART - Graphics Aperture Remapping "
806 "Table. It then performs manipulations in that range as if "
807 "that whole graphics aperture were part of its local memory. "
808 "A value of \"Both\" DMA and Execute models may also be "
809 "specified."),
810 ValueMap { "0", "1", "2", "3", "4" },
811 Values { "Unknown", "Other", "Execute", "DMA", "Both" }]
812 uint16 UsageModel;
813
814 [Description (
815 "An integer enumeration indicating the data transfer rate of "
816 "the graphics Controller."),
817 ValueMap { "0", "1", "2", "3", "4" },
818 Values { "Unknown", "Other", "1X", "2X", "4X" }]
819 uint16 DataTransferRate;
820 karl 1.1
821 [Description (
822 "An integer enumeration indicating the addressing mode of "
823 "the graphics Controller."),
824 ValueMap { "0", "1", "2", "3" },
825 Values { "Unknown", "Other", "Sideband", "Pipeline" }]
826 uint16 AddressingMode;
827
828 [Description (
829 "The maximum number of AGP Transaction requests that the "
830 "master (AGP Graphics Controller) is allowed to enqueue into "
831 "the target.")]
832 uint32 MaximumAGPCommandQueuePath;
833
834 [Description (
835 "The number of AGP Transaction that the core logic (chipset) "
836 "can accept into its transaction request queue from the "
837 "Controller.")]
838 uint32 MaxNumberOfPipelinedAGPTransactions;
839
840 [Description (
841 karl 1.1 "Size of the graphics aperture in KB."),
842 Units ( "KiloBytes" )]
843 uint32 GraphicsApertureSize;
844
845 [Description (
846 "A string containing the AGP specification version to which "
847 "this graphics Controller conforms.")]
848 string AGPSpecificationVersionConformance;
849 };
850
851
852 // ===================================================================
853 // VideoControllerResolution
854 // ===================================================================
855 [Version ( "2.6.0" ), Description (
856 "VideoControllerResolution describes the various video modes "
857 "that a VideoController can support. Video modes are defined by "
858 "the possible horizontal and vertical resolutions, refresh "
859 "rate, scan mode and number of colors settings supported by a "
860 "Controller. The actual resolutions, etc. that are in use, are "
861 "the values specified in the VideoController object.")]
862 karl 1.1 class CIM_VideoControllerResolution : CIM_Setting {
863
864 [Key, Override ( "SettingID" ), Description (
865 "The inherited SettingID serves as part of the key for a "
866 "VideoControllerResolution instance."),
867 MaxLen ( 256 )]
868 string SettingID;
869
870 [Description (
871 "Controller's horizontal resolution in Pixels."),
872 Units ( "Pixels" ),
873 MappingStrings { "MIF.DMTF|Monitor Resolutions|002.2" },
874 ModelCorrespondence {
875 "CIM_VideoController.CurrentHorizontalResolution" }]
876 uint32 HorizontalResolution;
877
878 [Description (
879 "Controller's vertical resolution in Pixels."),
880 Units ( "Pixels" ),
881 MappingStrings { "MIF.DMTF|Monitor Resolutions|002.3" },
882 ModelCorrespondence {
883 karl 1.1 "CIM_VideoController.CurrentVerticalResolution" }]
884 uint32 VerticalResolution;
885
886 [Description (
887 "Refresh rate in Hertz. If a range of rates is supported, "
888 "use the MinRefreshRate and MaxRefreshRate properties, and "
889 "set RefreshRate (this property) to 0."),
890 Units ( "Hertz" ),
891 MappingStrings { "MIF.DMTF|Monitor Resolutions|002.4" },
892 ModelCorrespondence { "CIM_VideoController.CurrentRefreshRate" }]
893 uint32 RefreshRate;
894
895 [Description (
896 "Minimum refresh rate in Hertz, when a range of rates is "
897 "supported at the specified resolutions."),
898 Units ( "Hertz" ),
899 MappingStrings { "MIF.DMTF|Monitor Resolutions|002.6" },
900 ModelCorrespondence { "CIM_VideoController.MinRefreshRate" }]
901 uint32 MinRefreshRate;
902
903 [Description (
904 karl 1.1 "Maximum refresh rate in Hertz, when a range of rates is "
905 "supported at the specified resolutions."),
906 Units ( "Hertz" ),
907 MappingStrings { "MIF.DMTF|Monitor Resolutions|002.7" },
908 ModelCorrespondence { "CIM_VideoController.MaxRefreshRate" }]
909 uint32 MaxRefreshRate;
910
911 [Description (
912 "Integer indicating whether the Controller operates in "
913 "interlaced (value=5) or non-interlaced (4) mode."),
914 ValueMap { "1", "2", "3", "4", "5" },
915 Values { "Other", "Unknown", "Not Supported",
916 "Non-Interlaced Operation", "Interlaced Operation" },
917 MappingStrings { "MIF.DMTF|Monitor Resolutions|002.5" },
918 ModelCorrespondence { "CIM_VideoController.CurrentScanMode" }]
919 uint16 ScanMode;
920
921 [Description (
922 "Number of colors supported at the current resolutions."),
923 ModelCorrespondence {
924 "CIM_VideoController.CurrentNumberOfColors" }]
925 karl 1.1 uint64 NumberOfColors;
926 };
927
928
929 // ===================================================================
930 // VideoSetting
931 // ===================================================================
932 [Association, Version ( "2.6.0" ), Description (
933 "VideoSetting associates the VideoControllerResolution Setting "
934 "with the Controller(s) to which it applies.")]
935 class CIM_VideoSetting : CIM_ElementSetting {
936
937 [Override ( "Element" ), Description (
938 "The VideoController.")]
939 CIM_VideoController REF Element;
940
941 [Override ( "Setting" ), Description (
942 "The resolutions, refresh rates, scan mode and number of "
943 "colors that can be set for the Controller.")]
944 CIM_VideoControllerResolution REF Setting;
945 };
946 karl 1.1
947
948 // ===================================================================
949 // PCIController
950 // ===================================================================
951 [Version ( "2.6.0" ), Description (
952 "PCIController is a superclass for the PCIBridge and PCIDevice "
953 "classes. These classes model adapters and bridges on a PCI "
954 "bus. The properties in PCIController and its subclasses are "
955 "defined in the various PCI Specifications published by the PCI "
956 "SIG.")]
957 class CIM_PCIController : CIM_Controller {
958
959 [Description (
960 "Current contents of the register that provides basic "
961 "control over the device's ability to respond to, and/or "
962 "perform PCI accesses.")]
963 uint16 CommandRegister;
964
965 [Description (
966 "An array of integers indicating controller capabilities. "
967 karl 1.1 "Information such as \"Supports 66MHz\" (value=2) is "
968 "specified in this property. The data in the Capabilities "
969 "array is gathered from the PCI Status Register and the PCI "
970 "Capabilities List as defined in the PCI Specification."),
971 ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8", "9",
972 "10", "11", "12" },
973 Values { "Unknown", "Other", "Supports 66MHz",
974 "Supports User Definable Features",
975 "Supports Fast Back-to-Back Transactions", "PCI-X Capable",
976 "PCI Power Management Supported",
977 "Message Signaled Interrupts Supported",
978 "Parity Error Recovery Capable", "AGP Supported",
979 // 10
980 "Vital Product Data Supported",
981 "Provides Slot Identification", "Hot Swap Supported" },
982 ArrayType ( "Indexed" ),
983 ModelCorrespondence { "CIM_PCIController.CapabilityDescriptions"
984 }]
985 uint16 Capabilities[];
986
987 [Description (
988 karl 1.1 "An array of free-form strings providing more detailed "
989 "explanations for any of the PCIController features "
990 "indicated in the Capabilities array. Note, each entry of "
991 "this array is related to the entry in the Capabilities "
992 "array that is located at the same index."),
993 ArrayType ( "Indexed" ),
994 ModelCorrespondence { "CIM_PCIController.Capabilities" }]
995 string CapabilityDescriptions[];
996
997 [Description (
998 "The slowest device select timing for a target device."),
999 ValueMap { "0", "1", "2", "3", "4", "5" },
1000 Values { "Unknown", "Other", "Fast", "Medium", "Slow",
1001 "Reserved" }]
1002 uint16 DeviceSelectTiming;
1003
1004 [Description (
1005 "Register of 8 bits that identifies the basic function of "
1006 "the PCI device. This is only the upper byte (offset 0Bh) of "
1007 "the 3 byte ClassCode field. Note that the property's "
1008 "ValueMap array specifies the decimal representation of this "
1009 karl 1.1 "information."),
1010 ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8", "9",
1011 "10", "11", "12", "13", "14", "15", "16", "17", "18..254",
1012 "255" },
1013 Values { "Pre 2.0", "Mass Storage", "Network", "Display",
1014 "Multimedia", "Memory", "Bridge", "Simple Communications",
1015 "Base Peripheral", "Input",
1016 // 10
1017 "Docking Station", "Processor", "Serial Bus", "Wireless",
1018 "Intelligent I/O", "Satellite Communication",
1019 "Encryption/Decryption",
1020 "Data Acquisition and Signal Processing",
1021 // 18 - 255
1022 "PCI Reserved", "Other" }]
1023 uint8 ClassCode;
1024
1025 [Description (
1026 "Specifies the system cache line size in doubleword "
1027 "increments (e.g., a 486-based system would store the value "
1028 "04h, indicating a cache line size of four doublewords."),
1029 Units ( "DoubleWords" )]
1030 karl 1.1 uint8 CacheLineSize;
1031
1032 [Description (
1033 "Defines the minimum amount of time, in PCI clock cycles, "
1034 "that the bus master can retain ownership of the bus."),
1035 Units ( "PCI clock cycles" )]
1036 uint8 LatencyTimer;
1037
1038 [Description (
1039 "Defines the PCI interrupt request pin (INTA# to INTD#) to "
1040 "which a PCI functional device is connected."),
1041 ValueMap { "0", "1", "2", "3", "4", "5" },
1042 Values { "None", "INTA#", "INTB#", "INTC#", "INTD#", "Unknown" }]
1043 uint16 InterruptPin;
1044
1045 [Description (
1046 "Doubleword Expansion ROM base memory address."),
1047 Units ( "DoubleWords" )]
1048 uint32 ExpansionROMBaseAddress;
1049
1050 [Description (
1051 karl 1.1 "Reports if the PCI device can perform the self test "
1052 "function. Returns bit 7 of the BIST register as a boolean.")]
1053 boolean SelfTestEnabled;
1054
1055 [Description (
1056 "Method to invoke PCI device self-test. This method sets bit "
1057 "6 of the BIST register. The return result is the lower four "
1058 "bits of the BIST register where 0 indicates success and "
1059 "non-zero is a device dependent failure. Support for this "
1060 "method is optional in the PCI Specification.")]
1061 uint8 BISTExecution( );
1062 };
1063
1064
1065 // ===================================================================
1066 // PCIDevice
1067 // ===================================================================
1068 [Version ( "2.6.0" ), Description (
1069 "Capabilities and management of a PCI device controller on an "
1070 "adapter card.")]
1071 class CIM_PCIDevice : CIM_PCIController {
1072 karl 1.1
1073 [Description (
1074 "Array of doubleword base memory addresses.")]
1075 uint32 BaseAddress[6];
1076
1077 [Description (
1078 "Subsystem identifier code.")]
1079 uint16 SubsystemID;
1080
1081 [Description (
1082 "Subsystem vendor ID. ID information is reported from a "
1083 "PCIDevice via protocol-specific requests. The correct place "
1084 "in the CIM Schema for this information is in CIM_Physical "
1085 "Element (the Manufacturer property) for hardware, and "
1086 "CIM_Product (the Vendor property) if the information is "
1087 "related to Product acquisition. This data is also reported "
1088 "here since it is part of the standard output from the "
1089 "Device, and as an optimization.")]
1090 uint16 SubsystemVendorID;
1091
1092 [Description (
1093 karl 1.1 "Register indiating how long the master would like to retain "
1094 "PCI bus ownership whenever it initiates a transaction. A "
1095 "zero value indicates no requirement."),
1096 Units ( "250 nanoseconds" )]
1097 uint8 MinGrantTime;
1098
1099 [Description (
1100 "Register specifying how often the device needs access to "
1101 "the PCI bus in 250ns. A zero value indicates no "
1102 "requirement."),
1103 Units ( "250 nanoseconds" )]
1104 uint8 MaxLatency;
1105 };
1106
1107
1108 // ===================================================================
1109 // PCIBridge
1110 // ===================================================================
1111 [Version ( "2.6.0" ), Description (
1112 "Capabilities and management of a PCI controller providing "
1113 "bridge to bridge capability.")]
1114 karl 1.1 class CIM_PCIBridge : CIM_PCIController {
1115
1116 [Description (
1117 "Array of doubleword base memory addresses.")]
1118 uint32 BaseAddress[2];
1119
1120 [Description (
1121 "The type of bridge. Except for \"Host\" (value=0), the type "
1122 "of bridge is PCI to <value>. For type \"Host\", the device "
1123 "is a Host to PCI bridge."),
1124 ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8", "128" },
1125 Values { "Host", "ISA", "EISA", "Micro Channel", "PCI",
1126 "PCMCIA", "NuBus", "CardBus", "RACEway",
1127 // 128
1128 "Other" }]
1129 uint16 BridgeType;
1130
1131 [Description (
1132 "The timeslice for the secondary interface when the bridge "
1133 "is acting as an initiator. A zero value indicates no "
1134 "requirement."),
1135 karl 1.1 Units ( "PCI clock cycles" )]
1136 uint8 SecondaryLatencyTimer;
1137
1138 [Description (
1139 "The number of the highest numbered bus that exists behind "
1140 "the bridge.")]
1141 uint8 SubordinateBusNumber;
1142
1143 [Description (
1144 "The number of the PCI bus segment to which the secondary "
1145 "interface of the bridge is connected.")]
1146 uint8 SecondayBusNumber;
1147
1148 [Description (
1149 "The number of the PCI bus segment to which the primary "
1150 "interface of the bridge is connected.")]
1151 uint8 PrimaryBusNumber;
1152
1153 [Description (
1154 "The contents of the Bridge's SecondaryStatusRegister. For "
1155 "more information on the contents of this register, refer to "
1156 karl 1.1 "the PCI-to-PCI Bridge Architecture Specification.")]
1157 uint16 SecondaryStatusRegister;
1158
1159 [Description (
1160 "The slowest device select timing for a target device on the "
1161 "secondary bus."),
1162 ValueMap { "0", "1", "2", "3", "4", "5" },
1163 Values { "Unknown", "Other", "Fast", "Medium", "Slow",
1164 "Reserved" }]
1165 uint16 SecondaryBusDeviceSelectTiming;
1166
1167 [Description (
1168 "End address of the I/O addresses supported by the bus. The "
1169 "upper four bits of this property specify the address bits, "
1170 "AD[15::12], of the I/O address. The remaining 12 bits of "
1171 "the I/O address are assumed to be all 1's.")]
1172 uint8 IOLimit;
1173
1174 [Description (
1175 "Base address of I/O addresses supported by the bus. The "
1176 "upper four bits of this property specify the address bits, "
1177 karl 1.1 "AD[15::12], of the I/O address. The remaining 12 bits of "
1178 "the I/O address are assumed to be 0.")]
1179 uint8 IOBase;
1180
1181 [Description (
1182 "End address of the memory supported by the bus. The upper "
1183 "twelve bits of this property specify the address bits, "
1184 "AD[31::20], of a 32-bit memory address. The remaining 20 "
1185 "bits of the address are assumed to be all 1's.")]
1186 uint16 MemoryLimit;
1187
1188 [Description (
1189 "Base address of the memory supported by the bus. The upper "
1190 "twelve bits of this property specify the address bits, "
1191 "AD[31::20], of a 32-bit memory address. The remaining 20 "
1192 "bits of the address are assumed to be 0.")]
1193 uint16 MemoryBase;
1194
1195 [Description (
1196 "End address of the memory that can be prefetched by the "
1197 "bus. The upper twelve bits of this property specify the "
1198 karl 1.1 "address bits, AD[31::20], of a 32-bit memory address. The "
1199 "remaining 20 bits of the address are assumed to be all 1's.")]
1200 uint16 PrefetchMemoryLimit;
1201
1202 [Description (
1203 "Base address of the memory that can be prefetched by the "
1204 "bus. The upper twelve bits of this property specify the "
1205 "address bits, AD[31::20], of a 32-bit memory address. The "
1206 "remaining 20 bits of the address are assumed to be 0.")]
1207 uint16 PrefetchMemoryBase;
1208
1209 [Description (
1210 "Upper 32 bits of the supported prefetch end address when "
1211 "64-bit addressing is used. The lower 32 bits are assumed to "
1212 "be all 1's.")]
1213 uint32 PrefetchLimitUpper32;
1214
1215 [Description (
1216 "Upper 32 bits of the supported prefetch base address when "
1217 "64-bit addressing is used. The lower 32 bits are assumed to "
1218 "be 0.")]
1219 karl 1.1 uint32 PrefetchBaseUpper32;
1220
1221 [Description (
1222 "Upper 16 bits of the supported I/O end address when 32-bit "
1223 "I/O addressing is used. The lower 16 bits are assumed to be "
1224 "all 1's.")]
1225 uint16 IOLimitUpper16;
1226
1227 [Description (
1228 "Upper 16 bits of the supported I/O base address when 32-bit "
1229 "I/O addressing is used. The lower 16 bits are assumed to be "
1230 "0.")]
1231 uint16 IOBaseUpper16;
1232 };
1233
1234
1235 // ==================================================================
1236 // PortController
1237 // ==================================================================
1238 [Version ( "2.8.0" ), Description (
1239 "PortController is a logical device corresponding to a hardware "
1240 karl 1.1 "network port controller. Port controllers provide various "
1241 "features depending on their types and versions.")]
1242 class CIM_PortController : CIM_Controller {
1243
1244 [Description (
1245 "The type or model of the port controller. Specific values "
1246 "will be enumerated in a later release of this schema. When "
1247 "set to 1 (\"Other\"), the related property "
1248 "OtherControllerType contains a string description of the "
1249 "controller's type."),
1250 ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8" },
1251 Values { "Unknown", "Other", "Ethernet", "IB", "FC", "FDDI",
1252 "ATM", "Token Ring", "Frame Relay" },
1253 ModelCorrespondence { "CIM_PortController.OtherControllerType" }]
1254 uint16 ControllerType;
1255
1256 [Description (
1257 "A string value for controller types not captured by the "
1258 "ControllerType enumeration. This should only be used when "
1259 "the value of the ControllerType property is set to 1, "
1260 "\"Other\"."),
1261 karl 1.1 ModelCorrespondence { "CIM_PortController.ControllerType" }]
1262 string OtherControllerType;
1263
1264 [Description (
1265 "The revision number of the controller.")]
1266 uint16 ControllerVersion;
1267 };
1268
1269
1270 // ===================================================================
1271 // end of file
1272 // ===================================================================
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