1 karl 1.1 // ===================================================================
2 // Title: Device Controller 2.7
3 // Filename: Device27_Contoller.mof
4 // Version: 2.7.1
5 // Release: Preliminary
6 // Date: November 12 2002
7 // ===================================================================
8 // Copyright 2002 Distributed Management Task Force, Inc. (DMTF).
9 // All rights reserved.
10 // DMTF is a not-for-profit association of industry members dedicated
11 // to promoting enterprise and systems management and interoperability.
12 // DMTF specifications and documents may be reproduced for uses
13 // consistent with this purpose by members and non-members,
14 // provided that correct attribution is given.
15 // As DMTF specifications may be revised from time to time,
16 // the particular version and release date should always be noted.
17 //
18 // Implementation of certain elements of this standard or proposed
19 // standard may be subject to third party patent rights, including
20 // provisional patent rights (herein "patent rights"). DMTF makes
21 // no representations to users of the standard as to the existence
22 karl 1.1 // of such rights, and is not responsible to recognize, disclose, or
23 // identify any or all such third party patent right, owners or
24 // claimants, nor for any incomplete or inaccurate identification or
25 // disclosure of such rights, owners or claimants. DMTF shall have no
26 // liability to any party, in any manner or circumstance, under any
27 // legal theory whatsoever, for failure to recognize, disclose, or
28 // identify any such third party patent rights, or for such party's
29 // reliance on the standard or incorporation thereof in its product,
30 // protocols or testing procedures. DMTF shall have no liability to
31 // any party implementing such standard, whether such implementation
32 // is foreseeable or not, nor to any patent owner or claimant, and shall
33 // have no liability or responsibility for costs or losses incurred if
34 // a standard is withdrawn or modified after publication, and shall be
35 // indemnified and held harmless by any party implementing the
36 // standard from any and all claims of infringement by a patent owner
37 // for such implementations.
38 //
39 // For information about patents held by third-parties which have
40 // notified the DMTF that, in their opinion, such patent may relate to
41 // or impact implementations of DMTF standards, visit
42 // http://www.dmtf.org/about/policies/disclosures.php.
43 karl 1.1 // ===================================================================
44 // Description: The Device Model extends the management concepts that
45 // are related to LogicalDevices. This file defines
46 // the concepts and classes for Controllers.
47 //
48 // The object classes below are listed in an order that
49 // avoids forward references. Required objects, defined
50 // by other working groups, are omitted.
51 // ==================================================================
52 // Change Log for v2.7.1
53 // CR920 - Add missing parenthesis to the Description for PCIController.
54 // CacheLineSize
55 //
56 // Change Log for v2.7
57 // CR622 - Fix the DMI mapping string to include the attribute number
58 // for Controller.ProtocolSupported, .MaxNumberControlled, &
59 // .ProtocolDescription,
60 // SCSIController.MaxDataWidth & .MaxTransferRate,
61 // SCSIInterface.InitiatorId, .TargetId & .SCSISignal
62 // CR632 - Add PortController
63 // CR654 - Update the description for Controller
64 karl 1.1 // - Add Controller.PortNumber
65 // - Update the Description for ControlledBy
66 // - Add ControlledBy.DeviceNumber
67 // - Add SCSILUN
68 // CR830 - Update the Description for ControlledBy
69 // - Modify type of ControlledBy.DeviceNumber from uint64 to
70 // a string
71 // - Add ControlledBy.AccessMode and ControlledBy.AccessPriority
72 // - Update SCSILUN.DeviceNumber to match change to ContolledBy
73 // CR892 - Fix the subclassing inconsistency of VideoController
74 // ==================================================================
75
76 #pragma locale ("en_US")
77
78
79 // ===================================================================
80 // Controller
81 // ===================================================================
82 [Abstract, Version ("2.7.0"), Description (
83 "Controller is a superclass for grouping the miscellaneous "
84 "control-related Devices that exist. Examples of Controllers "
85 karl 1.1 "are SCSIControllers, USBControllers, SerialControllers, ... "
86 "The Controller class is an abstraction for Devices with a "
87 "single protocol stack, which exist to control communications "
88 "(data, control, and reset) with devices.") ]
89 class CIM_Controller : CIM_LogicalDevice {
90
91 [Experimental, Description (
92 "System level port or bus identification number.") ]
93 uint64 PortNumber;
94
95 [Description (
96 "Time of last reset of the Controller.") ]
97 datetime TimeOfLastReset;
98
99 [Description (
100 "The protocol used by the Controller to access 'controlled' "
101 "Devices."),
102 ValueMap {"1", "2", "3", "4", "5", "6", "7", "8", "9", "10",
103 "11", "12", "13", "14", "15", "16", "17", "18", "19",
104 "20", "21", "22", "23", "24", "25", "26", "27", "28",
105 "29", "30", "31", "32", "33", "34", "35", "36", "37",
106 karl 1.1 "38", "39", "40", "41", "42", "43", "44", "45", "46",
107 "47"},
108 Values {"Other", "Unknown", "EISA", "ISA", "PCI", "ATA/ATAPI",
109 "Flexible Diskette", "1496", "SCSI Parallel Interface",
110 // 10
111 "SCSI Fibre Channel Protocol", "SCSI Serial Bus Protocol",
112 "SCSI Serial Bus Protocol-2 (1394)",
113 "SCSI Serial Storage Architecture", "VESA", "PCMCIA",
114 "Universal Serial Bus", "Parallel Protocol", "ESCON",
115 "Diagnostic",
116 // 20
117 "I2C", "Power", "HIPPI", "MultiBus", "VME",
118 "IPI", "IEEE-488", "RS232", "IEEE 802.3 10BASE5",
119 "IEEE 802.3 10BASE2",
120 // 30
121 "IEEE 802.3 1BASE5",
122 "IEEE 802.3 10BROAD36", "IEEE 802.3 100BASEVG",
123 "IEEE 802.5 Token-Ring", "ANSI X3T9.5 FDDI", "MCA",
124 "ESDI", "IDE", "CMD", "ST506",
125 // 40
126 "DSSI", "QIC2",
127 karl 1.1 "Enhanced ATA/IDE", "AGP", "TWIRP (two-way infrared)",
128 "FIR (fast infrared)", "SIR (serial infrared)",
129 "IrBus"},
130 MappingStrings {"MIF.DMTF|Bus Port|004.2",
131 "MIF.DMTF|Disks|003.3"},
132 ModelCorrespondence {"CIM_Controller.ProtocolDescription"} ]
133 uint16 ProtocolSupported;
134
135 [Description (
136 "Maximum number of directly addressable entities supported "
137 "by this Controller. A value of 0 should be used if the "
138 "number is unknown or unlimited."),
139 MappingStrings {"MIF.DMTF|Bus Port|004.9"} ]
140 uint32 MaxNumberControlled;
141
142 [Description (
143 "A free form string providing more information related "
144 "to the ProtocolSupported by the Controller."),
145 ModelCorrespondence {"CIM_Controller.ProtocolSupported"},
146 MappingStrings {"MIF.DMTF|Bus Port|004.3"} ]
147 string ProtocolDescription;
148 karl 1.1 };
149
150
151 // ===================================================================
152 // ControlledBy
153 // ===================================================================
154 [Association, Version ("2.7.0"), Description (
155 "The association indicates a relationship between a Storage"
156 "Volume exposed as a LUN through a slave SCSI Controller. "
157 "A new relationship is required in order to distinguish "
158 "between the 'Host' connection (represented by SCSIInterface) "
159 "and the 'Target' connection (represented by SCSILUN).") ]
160 class CIM_ControlledBy : CIM_DeviceConnection {
161
162 [Override ("Antecedent"),
163 Description ("The Controller.") ]
164 CIM_Controller REF Antecedent;
165
166 [Override ("Dependent"),
167 Description ("The controlled Device.") ]
168 CIM_LogicalDevice REF Dependent;
169 karl 1.1
170 [Experimental, Description (
171 "Address of associated Device in context of the "
172 "antecedent Controller.") ]
173 string DeviceNumber;
174
175 [Experimental, Description (
176 "This property describes the accessibility of the device "
177 "thru the antedecent controller."),
178 ValueMap {"2", "3", "4"},
179 Values {"ReadWrite", "ReadOnly", "NoAccess"} ]
180 uint16 AccessMode;
181
182 [Experimental, Description (
183 "The property describes the priority given to accesses of "
184 "the device thru this controller. The highest priority path "
185 "will have the lowest value for this parameter.") ]
186 uint16 AccessPriority;
187
188 [Description (
189 "The State property indicates whether the Controller is "
190 karl 1.1 "actively commanding or accessing the Device (value=1) or "
191 "not (value=2). Also, the value, \"Unknown\" (0), can be "
192 "defined. This information is necessary when a LogicalDevice "
193 "can be commanded by, or accessed through, multiple "
194 "Controllers."),
195 ValueMap {"0", "1", "2"},
196 Values {"Unknown", "Active", "Inactive"} ]
197 uint16 AccessState;
198
199 [Description (
200 "The time that the downstream Device was last reset by "
201 "the Controller.") ]
202 datetime TimeOfDeviceReset;
203
204 [Description (
205 "Number of hard resets issued by the Controller. A hard reset "
206 "returns the Device to its initialization or 'boot-up' state. "
207 "All internal Device state information and data are lost."),
208 Counter ]
209 uint32 NumberOfHardResets;
210
211 karl 1.1 [Description (
212 "Number of soft resets issued by the Controller. A soft "
213 "reset does not completely clear current Device state and/or "
214 "data. Exact semantics are dependent on the Device, and on "
215 "the protocols and mechanisms used to communicate to it."),
216 Counter ]
217 uint32 NumberOfSoftResets;
218 };
219
220
221 // ===================================================================
222 // ESCONController
223 // ===================================================================
224 [Version ("2.6.0"), Description (
225 "Capabilities and management of an ESCONController.") ]
226 class CIM_ESCONController : CIM_Controller {
227 };
228
229
230 // ===================================================================
231 // IDEController
232 karl 1.1 // ===================================================================
233 [Version ("2.6.0"), Description (
234 "Capabilities and management of an IDEController.") ]
235 class CIM_IDEController : CIM_Controller {
236 };
237
238
239 // ===================================================================
240 // InfraredController
241 // ===================================================================
242 [Version ("2.6.0"), Description (
243 "Capabilities and management of an InfraredController.") ]
244 class CIM_InfraredController : CIM_Controller {
245 };
246
247
248 // ===================================================================
249 // ManagementController
250 // ===================================================================
251 [Version ("2.6.0"), Description (
252 "Capabilities and managment of a ManagementController. An I2C "
253 karl 1.1 "microcontroller is a type of ManagementController.") ]
254 class CIM_ManagementController : CIM_Controller {
255 };
256
257
258 // ===================================================================
259 // ParallelController
260 // ===================================================================
261 [Version ("2.6.0"), Description (
262 "Capabilities and management of the ParallelController.") ]
263 class CIM_ParallelController : CIM_Controller {
264
265 [Description (
266 "Set to true if the ParallelController supports DMA."),
267 MappingStrings {"MIF.DMTF|Parallel Ports|003.7"} ]
268 boolean DMASupport;
269
270 [Description (
271 "An integer enumeration indicating the capabilities of the "
272 "ParallelController."),
273 ArrayType ("Indexed"),
274 karl 1.1 ValueMap {"0", "1", "2", "3", "4", "5", "6", "7", "8"},
275 Values {"Unknown", "Other", "XT/AT Compatible",
276 "PS/2 Compatible", "ECP", "EPP", "PC-98",
277 "PC-98-Hireso", "PC-H98"},
278 MappingStrings {"MIF.DMTF|Parallel Ports|003.8"},
279 ModelCorrespondence {
280 "CIM_ParallelController.CapabilityDescriptions"} ]
281 uint16 Capabilities[];
282
283 [Description (
284 "An array of free-form strings providing more detailed "
285 "explanations for any of the ParallelController features "
286 "indicated in the Capabilities array. Note, each entry of "
287 "this array is related to the entry in the Capabilities "
288 "array that is located at the same index."),
289 ArrayType ("Indexed"),
290 ModelCorrespondence {"CIM_ParallelController.Capabilities"} ]
291 string CapabilityDescriptions[];
292
293 [Description (
294 "An enumeration indicating the operational security for the "
295 karl 1.1 "Controller. For example, information that the Device's "
296 "external interface is locked out (value=4) or \"Boot "
297 "Bypass\" (value=6) can be described using this property."),
298 ValueMap {"1", "2", "3", "4", "5", "6"},
299 Values {"Other", "Unknown", "None",
300 "External Interface Locked Out",
301 "External Interface Enabled", "Boot Bypass"},
302 MappingStrings {"MIF.DMTF|Parallel Ports|003.10"} ]
303 uint16 Security;
304 };
305
306
307 // ===================================================================
308 // PCMCIAController
309 // ===================================================================
310 [Version ("2.6.0"), Description (
311 "Capabilities and management of a PCMCIAController.") ]
312 class CIM_PCMCIAController : CIM_Controller {
313 };
314
315
316 karl 1.1 // ==================================================================
317 // PortController
318 // ==================================================================
319 [Experimental, Version ("2.7.0"), Description (
320 "PortController is a logical device corresponding to a hardware "
321 "network port controller. Port controllers provide various "
322 "features depending on their types and versions.") ]
323 class CIM_PortController : CIM_Controller {
324
325 [Description (
326 "The type or model of the port controller. Specific "
327 "values will be enumerated in a later release of this "
328 "schema. When set to 1 (\"Other\"), the related property "
329 "OtherControllerType contains a string description of "
330 "the controller's type."),
331 ValueMap {"0", "1", "2", "3", "4", "5", "6", "7", "8"},
332 Values {"Unknown", "Other", "Ethernet", "IB", "FC",
333 "FDDI", "ATM", "Token Ring", "Frame Relay"},
334 ModelCorrespondence {
335 "CIM_PortController.OtherControllerType"} ]
336 uint16 ControllerType;
337 karl 1.1
338 [Description (
339 "A string value for controller types not captured by the "
340 "ControllerType enumeration. This should only be used "
341 "when the value of the ControllerType property is "
342 "set to 1, \"Other\"."),
343 ModelCorrespondence {
344 "CIM_PortController.ControllerType"} ]
345 string OtherControllerType;
346
347 [Description (
348 "The revision number of the controller.") ]
349 uint16 ControllerVersion;
350 };
351
352
353 // ===================================================================
354 // SCSIController
355 // ===================================================================
356 [Version ("2.7.0"), Description (
357 "Capabilities and management of the SCSIController.") ]
358 karl 1.1 class CIM_SCSIController : CIM_Controller {
359
360 [Description (
361 "An integer enumeration indicating whether or not the "
362 "SCSIController provides redundancy or protection against "
363 "device failures."),
364 ValueMap {"1", "2", "3", "4", "5", "6"},
365 Values {"Other", "Unknown", "Unprotected", "Protected",
366 "Protected through SCC (SCSI-3 Controller Command)",
367 "Protected through SCC-2 (SCSI-3 Controller Command)"},
368 MappingStrings {"MIF.DMTF|Storage Controller|001.3"} ]
369 uint16 ProtectionManagement;
370
371 [Description (
372 "Maximum data width (in bits) supported by the SCSI"
373 "Controller."),
374 Units ("Bits"),
375 MappingStrings {"MIF.DMTF|Bus Port|004.7"} ]
376 uint32 MaxDataWidth;
377
378 [Description (
379 karl 1.1 "Maximum transfer rate (in Bits per Second) supported by the "
380 "SCSIController."),
381 Units ("Bits per Second"),
382 MappingStrings {"MIF.DMTF|Bus Port|004.8"} ]
383 uint64 MaxTransferRate;
384
385 [Description (
386 "Number of SCSIController timeouts that have occurred since "
387 "the TimeOfLastReset."),
388 Counter ]
389 uint32 ControllerTimeouts;
390
391 [Description (
392 "Signal capabilities that can be supported by the SCSI"
393 "Controller. For example, the Controller may support "
394 "\"Single Ended\" and \"Differential\". In this case, the "
395 "values 3 and 4 would be written to the Signal"
396 "Capabilities array."),
397 ValueMap {"1", "2", "3", "4", "5", "6"},
398 Values {"Other", "Unknown", "Single Ended", "Differential",
399 "Low Voltage Differential", "Optical"},
400 karl 1.1 ModelCorrespondence {"CIM_SCSIInterface.SCSISignal"} ]
401 uint16 SignalCapabilities[];
402 };
403
404
405 // ===================================================================
406 // SCSIInterface
407 // ===================================================================
408 [Association, Version ("2.7.0"), Description (
409 "SCSIInterface is a ControlledBy relationship indicating "
410 "which Devices are accessed through a SCSIController and "
411 "the characteristics of this access.") ]
412 class CIM_SCSIInterface : CIM_ControlledBy {
413
414 [Override ("Antecedent"),
415 Description ("The SCSIController.") ]
416 CIM_SCSIController REF Antecedent;
417
418 [Description (
419 "Number of SCSI timeouts that have occurred since last hard "
420 "or soft reset related to the controlled Device. The time of "
421 karl 1.1 "last reset is indicated in the TimeOfDeviceReset property, "
422 "inherited from the ControlledBy association."),
423 Counter ]
424 uint32 SCSITimeouts;
425
426 [Description (
427 "Number of SCSI retries that have occurred since last hard "
428 "or soft reset related to the controlled Device. The time of "
429 "last reset is indicated in the TimeOfDeviceReset property, "
430 "inherited from the ControlledBy association."),
431 Counter,
432 MappingStrings {"MIF.DMTF|Mass Storage Statistics|001.18"} ]
433 uint32 SCSIRetries;
434
435 [Description ("The SCSI Initiator ID."),
436 MappingStrings {"MIF.DMTF|Bus Port|004.5"} ]
437 uint32 InitiatorId;
438
439 [Description ("The SCSI Target ID."),
440 MappingStrings {"MIF.DMTF|Bus Port|004.5"} ]
441 uint32 TargetId;
442 karl 1.1
443 [Description ("The SCSI Target LUN."),
444 MappingStrings {"MIF.DMTF|Storage Devices|001.4"} ]
445 uint64 TargetLUN;
446
447 [Description (
448 "SCSIReservation indicates the type of SCSI reservation "
449 "that currently exists between the source and destination."),
450 ValueMap {"0", "1", "2", "3"},
451 Values {"Unknown", "None", "Simple", "Persistent"} ]
452 uint16 SCSIReservation;
453
454 [Description (
455 "The SCSI signal characteristics being used for this "
456 "connection. The value listed here must also be listed in "
457 "the SCSIController's SignalCapabilities field."),
458 ValueMap {"1", "2", "3", "4", "5", "6"},
459 Values {"Other", "Unknown", "Single Ended", "Differential",
460 "Low Voltage Differential", "Optical"},
461 MappingStrings {"MIF.DMTF|Bus Port|004.4"},
462 ModelCorrespondence {"CIM_SCSIController.SignalCapabilities"} ]
463 karl 1.1 uint16 SCSISignal;
464
465 [Description (
466 "Maximum number of Command Descriptor Blocks (CDBs) that "
467 "can be supported by the target. This data can not be "
468 "obtained under all circumstances.") ]
469 uint32 MaxQueueDepth;
470
471 [Description (
472 "The maximum number of concurrent Command Descriptor Blocks "
473 "(CDBs) that the initiator will send to the target. This "
474 "value should never be greater than MaxQueueDepth.") ]
475 uint32 QueueDepthLimit;
476 };
477
478
479 // ===================================================================
480 // SCSILUN
481 // ===================================================================
482 [Association, Experimental, Version ("2.7.0"), Description (
483 "The association indicates a relationship between a Storage"
484 karl 1.1 "Volume exposed as a LUN through a slave SCSI Controller. "
485 "A new relationship is required in order to distinguish "
486 "between the 'Host' connection (represented by SCSIInterface) "
487 "and the 'Target' connection (represented by SCSILUN).") ]
488 class CIM_SCSILUN : CIM_ControlledBy {
489
490 [Override ("Antecedent"),
491 Description ("The SCSIController.") ]
492 CIM_SCSIController REF Antecedent;
493
494 [Override ("DeviceNumber"), Description (
495 "LUN Identifier assigned to the target device.") ]
496 string DeviceNumber;
497 };
498
499
500 // ===================================================================
501 // SerialController
502 // ===================================================================
503 [Version ("2.6.0"), Description (
504 "Capabilities and management of the SerialController.") ]
505 karl 1.1 class CIM_SerialController : CIM_Controller {
506
507 [Description (
508 "The Capabilities property defines chip level compatibility "
509 "for the SerialController. Therefore, this property describes "
510 "the buffering and other capabilities of the SerialController, "
511 "that may be inherent in the chip hardware. The property is "
512 "an enumerated integer."),
513 ArrayType ("Indexed"),
514 ValueMap {"1", "2", "3", "4", "5", "6",
515 "160", "161"},
516 Values {"Other", "Unknown", "XT/AT Compatible",
517 "16450 Compatible", "16550 Compatible",
518 "16550A Compatible",
519 // 160
520 "8251 Compatible",
521 "8251FIFO Compatible"},
522 MappingStrings {"MIF.DMTF|Serial Ports|004.7"},
523 ModelCorrespondence {
524 "CIM_SerialController.CapabilityDescriptions"} ]
525 uint16 Capabilities[];
526 karl 1.1
527 [Description (
528 "An array of free-form strings providing more detailed "
529 "explanations for any of the SerialController features "
530 "indicated in the Capabilities array. Note, each entry of "
531 "this array is related to the entry in the Capabilities "
532 "array that is located at the same index."),
533 ArrayType ("Indexed"),
534 ModelCorrespondence {"CIM_SerialController.Capabilities"} ]
535 string CapabilityDescriptions[];
536
537 [Description (
538 "Maximum baud rate in Bits per Second supported by the "
539 "SerialController."),
540 Units ("Bits per Second"),
541 MappingStrings {"MIF.DMTF|Serial Ports|004.6"} ]
542 uint32 MaxBaudRate;
543
544 [Description (
545 "An enumeration indicating the operational security for the "
546 "Controller. For example, information that the Device's "
547 karl 1.1 "external interface is locked out (value=4) or \"Boot "
548 "Bypass\" (value=6) can be described using this property."),
549 ValueMap {"1", "2", "3", "4", "5", "6"},
550 Values {"Other", "Unknown", "None",
551 "External Interface Locked Out",
552 "External Interface Enabled", "Boot Bypass"},
553 MappingStrings {"MIF.DMTF|Serial Ports|004.9"} ]
554 uint16 Security;
555 };
556
557
558 // ===================================================================
559 // SerialInterface
560 // ===================================================================
561 [Association, Version ("2.6.0"), Description (
562 "SerialInterface is a ControlledBy relationship indicating "
563 "which Devices are accessed through the SerialController and "
564 "the characteristics of this access.") ]
565 class CIM_SerialInterface : CIM_ControlledBy {
566
567 [Override ("Antecedent"), Description (
568 karl 1.1 "The SerialController.") ]
569 CIM_SerialController REF Antecedent;
570
571 [Override ("NegotiatedDataWidth"), Description (
572 "For the SerialInterface, NegotiatedDataWidth is the number "
573 "of data bits to be transmitted, without stop bits or parity."),
574 Units ("Bits") ]
575 uint32 NegotiatedDataWidth;
576
577 [Description ("Number of stop bits to be transmitted."),
578 Units ("Bits") ]
579 uint16 NumberOfStopBits;
580
581 [Description (
582 "Information on the parity setting for transmitted data. "
583 "No parity (value=1), even (2) or odd (3) can be specified."),
584 ValueMap {"0", "1", "2", "3"},
585 Values {"Unknown", "None", "Even", "Odd"} ]
586 uint16 ParityInfo;
587
588 [Description (
589 karl 1.1 "An integer enumeration indicating the flow control "
590 "(Xon-Xoff and/or RTS/CTS) for transmitted data."),
591 ValueMap {"0", "1", "2", "3", "4", "5"},
592 Values {"Unknown", "Not Supported", "None", "XonXoff",
593 "RTS/CTS", "Both XonXoff and RTS/CTS"} ]
594 uint16 FlowControlInfo;
595 };
596
597
598 // ===================================================================
599 // SSAController
600 // ===================================================================
601 [Version ("2.6.0"), Description (
602 "Capabilities and management of an SSAController (Serial "
603 "Storage Architecture).") ]
604 class CIM_SSAController : CIM_Controller {
605 };
606
607
608 // ===================================================================
609 // USBController
610 karl 1.1 // ===================================================================
611 [Version ("2.6.0"), Description (
612 "Capabilities and managment of a USB Host Controller.") ]
613 class CIM_USBController : CIM_Controller {
614
615 [Description (
616 "Indicates the latest USB Version supported by the Controller. "
617 "The property is expressed as a Binary-Coded Decimal (BCD) "
618 "where a decimal point is implied between the 2nd and 3rd "
619 "digits. For example, a value of 0x201 indicates that "
620 "version 2.01 is supported.") ]
621 uint16 USBVersion;
622
623 [Description (
624 "The type of interface used between the host system software "
625 "and the USBController."),
626 ValueMap {"0", "1", "2", "3"},
627 Values {"Unknown", "Other", "UHCI", "OHCI"},
628 ModelCorrespondence {"CIM_USBController.ControllerVersion"} ]
629 uint16 InterfaceType;
630
631 karl 1.1 [Description (
632 "Indicates the version of the USB Host Controller register "
633 "set, specific to the InterfaceType. The property is "
634 "expressed as a Binary-Coded Decimal (BCD) value where a "
635 "decimal point is implied between the 2nd and 3rd digits. "
636 "For example, a value of 0x103 indicates that version "
637 "1.03 is supported."),
638 ModelCorrespondence {"CIM_USBController.InterfaceType"} ]
639 uint16 ControllerVersion;
640 };
641
642
643 // ===================================================================
644 // VideoController
645 // ===================================================================
646 [Version ("2.7.0"), Description (
647 "Capabilities and management of the VideoController.") ]
648 class CIM_VideoController : CIM_Controller {
649
650 [Override ("Description"),
651 MappingStrings {"MIF.DMTF|Video|004.18"} ]
652 karl 1.1 string Description;
653
654 [Description (
655 "A free-form string describing the video "
656 "processor/Controller.") ]
657 string VideoProcessor;
658
659 [Description (
660 "An integer enumeration indicating the type of video memory."),
661 ValueMap {"1", "2", "3", "4", "5", "6", "7", "8", "9",
662 "10", "11", "12", "13"},
663 Values {"Other", "Unknown", "VRAM", "DRAM", "SRAM", "WRAM",
664 "EDO RAM", "Burst Synchronous DRAM",
665 "Pipelined Burst SRAM",
666 //10
667 "CDRAM", "3DRAM", "SDRAM", "SGRAM"},
668 MappingStrings {"MIF.DMTF|Video|004.6"} ]
669 uint16 VideoMemoryType;
670
671 [Description (
672 "Number of video pages supported given the current resolutions "
673 karl 1.1 "and available memory.") ]
674 uint32 NumberOfVideoPages;
675
676 [Description ("Maximum amount of memory supported in bytes."),
677 Units ("Bytes") ]
678 uint32 MaxMemorySupported;
679
680 [Description (
681 "An array of integers indicating the graphics and 3D "
682 "capabilities of the VideoController."),
683 ValueMap {"0", "1", "2", "3", "4", "5", "6", "7", "8"},
684 Values {"Unknown", "Other", "Graphics Accelerator",
685 "3D Accelerator", "PCI Fast Write",
686 "MultiMonitor Support", "PCI Mastering",
687 "Second Monochrome Adapter Support",
688 "Large Memory Address Support"},
689 ModelCorrespondence {
690 "CIM_VideoController.CapabilityDescriptions"} ]
691 uint16 AcceleratorCapabilities[];
692
693 [Description (
694 karl 1.1 "An array of free-form strings providing more detailed "
695 "explanations for any of the video Accelerator features "
696 "indicated in the Capabilities array. Note, each entry "
697 "of this array is related to the entry in the Capabilities "
698 "array that is located at the same index."),
699 ArrayType ("Indexed"),
700 ModelCorrespondence {
701 "CIM_VideoController.AcceleratorCapabilities"} ]
702 string CapabilityDescriptions[];
703
704 [Description ("The number of bits used to display each pixel."),
705 Units ("Bits"),
706 MappingStrings {"MIF.DMTF|Video|004.12"} ]
707 uint32 CurrentBitsPerPixel;
708
709 [Description ("Current number of horizontal pixels."),
710 Units ("Pixels"),
711 MappingStrings {"MIF.DMTF|Video|004.11"} ]
712 uint32 CurrentHorizontalResolution;
713
714 [Description ("Current number of vertical pixels."),
715 karl 1.1 Units ("Pixels"),
716 MappingStrings {"MIF.DMTF|Video|004.10"} ]
717 uint32 CurrentVerticalResolution;
718
719 [Description (
720 "Maximum refresh rate of the VideoController in Hertz."),
721 Units ("Hertz"),
722 MappingStrings {"MIF.DMTF|Video|004.5"} ]
723 uint32 MaxRefreshRate;
724
725 [Description (
726 "Minimum refresh rate of the Video Controller in Hertz."),
727 Units ("Hertz"),
728 MappingStrings {"MIF.DMTF|Video|004.4"} ]
729 uint32 MinRefreshRate;
730
731 [Description ("Current refresh rate in Hertz."),
732 Units ("Hertz"),
733 MappingStrings {"MIF.DMTF|Video|004.15"} ]
734 uint32 CurrentRefreshRate;
735
736 karl 1.1 [Description (
737 "Current scan mode. \"Interlaced\" (value=3) or "
738 "\"Non Interlaced\" (4) can be defined using this property."),
739 ValueMap {"1", "2", "3", "4"},
740 Values {"Other", "Unknown", "Interlaced", "Non Interlaced"},
741 MappingStrings {"MIF.DMTF|Video|004.8"} ]
742 uint16 CurrentScanMode;
743
744 [Description (
745 "If in character mode, number of rows for this Video"
746 "Controller. Otherwise, enter 0."),
747 MappingStrings {"MIF.DMTF|Video|004.13"} ]
748 uint32 CurrentNumberOfRows;
749
750 [Description (
751 "If in character mode, number of columns for this "
752 "VideoController. Otherwise, enter 0."),
753 MappingStrings {"MIF.DMTF|Video|004.14"} ]
754 uint32 CurrentNumberOfColumns;
755
756 [Description (
757 karl 1.1 "Number of colors supported at the current resolutions.") ]
758 uint64 CurrentNumberOfColors;
759 };
760
761
762 // ===================================================================
763 // PCVideoController
764 // ===================================================================
765 [Version ("2.6.0"), Description (
766 "Capabilities and management of a PCVideoController, a subtype "
767 "of VideoController.") ]
768 class CIM_PCVideoController : CIM_VideoController {
769
770 [Description (
771 "The video architecture. For example, VGA (value=5) or "
772 "PC-98 (160) may be specified."),
773 ValueMap {"1", "2", "3", "4", "5", "6", "7", "8", "9",
774 "10", "11", "12", "160"},
775 Values {"Other", "Unknown", "CGA", "EGA", "VGA", "SVGA", "MDA",
776 "HGC", "MCGA",
777 // 10
778 karl 1.1 "8514A", "XGA", "Linear Frame Buffer", "PC-98"},
779 MappingStrings {"MIF.DMTF|Video|004.2"} ]
780 uint16 VideoArchitecture;
781
782 [Description ("Current video mode."),
783 MappingStrings {"MIF.DMTF|Video|004.3"} ]
784 uint16 VideoMode;
785
786 [Description (
787 "Current number of color planes. If this value is not "
788 "applicable for the current video configuration, enter 0.") ]
789 uint16 NumberOfColorPlanes;
790 };
791
792
793 // ===================================================================
794 // AGPVideoController
795 // ===================================================================
796 [Version ("2.7.0"), Description (
797 "Capabilities and management of an AGPVideoController.") ]
798 class CIM_AGPVideoController: CIM_VideoController {
799 karl 1.1
800 [Deprecated {"VideoController.AcceleratorCapabilities"},
801 Description (
802 "This property has been incorporated into the inherited "
803 "AcceleratorCapabilities property. "
804 "Capabilities of the AGP Graphics Controller. For example, "
805 "the Device may support multiple monitors, PCI Mastering and "
806 "large memory addresses. In this case, the values 3, 4 and 6 "
807 "would be written to the Capabilities array."),
808 ArrayType("Indexed"),
809 ValueMap {"0", "1", "2", "3", "4", "5", "6"},
810 Values {"Unknown", "Other", "PCI Fast Write",
811 "MultiMonitor Support", "PCI Mastering",
812 "Second Monochrome Adapter Support",
813 "Large Memory Address Support"},
814 ModelCorrespondence {
815 "CIM_AGPVideoController.CapabilityDescriptions"} ]
816 uint16 Capabilities[];
817
818 [Description (
819 "Size of the non-local video memory in KB."),
820 karl 1.1 Units ("KiloBytes") ]
821 uint32 NonlocalVideoMemorySize;
822
823 [Description (
824 "Width of the internal bus in the graphics Controller, in "
825 "bits."),
826 Units ("Bits") ]
827 uint32 LocalBusWidth;
828
829 [Description (
830 "An integer enumeration indicating the usage model of the "
831 "graphics Controller. Usage model indicates how the Controller "
832 "does manipulations of graphics surfaces, textures, etc. in "
833 "memory. DMA indicates that the graphics Controller brings "
834 "structures from the system memory to its local memory to "
835 "perform needed manipulations or renderings. Execute specifies "
836 "that the graphics Controller can directly access a specified "
837 "region in main memory (called the graphics aperture) using "
838 "GART - Graphics Aperture Remapping Table. It then performs "
839 "manipulations in that range as if that whole graphics "
840 "aperture were part of its local memory. A value of \"Both\" "
841 karl 1.1 "DMA and Execute models may also be specified."),
842 ValueMap {"0", "1", "2", "3", "4"},
843 Values {"Unknown", "Other", "Execute", "DMA", "Both"} ]
844 uint16 UsageModel;
845
846 [Description (
847 "An integer enumeration indicating the data transfer rate of "
848 "the graphics Controller."),
849 ValueMap {"0", "1", "2", "3", "4"},
850 Values {"Unknown", "Other", "1X", "2X", "4X"} ]
851 uint16 DataTransferRate;
852
853 [Description (
854 "An integer enumeration indicating the addressing mode of the "
855 "graphics Controller."),
856 ValueMap {"0", "1", "2", "3"},
857 Values {"Unknown", "Other", "Sideband", "Pipeline"} ]
858 uint16 AddressingMode;
859
860 [Description (
861 "The maximum number of AGP Transaction requests that the "
862 karl 1.1 "master (AGP Graphics Controller) is allowed to enqueue into "
863 "the target.") ]
864 uint32 MaximumAGPCommandQueuePath;
865
866 [Description (
867 "The number of AGP Transaction that the core logic (chipset) "
868 "can accept into its transaction request queue from the "
869 "Controller.") ]
870 uint32 MaxNumberOfPipelinedAGPTransactions;
871
872 [Description ("Size of the graphics aperture in KB."),
873 Units ("KiloBytes") ]
874 uint32 GraphicsApertureSize;
875
876 [Description (
877 "A string containing the AGP specification version to which "
878 "this graphics Controller conforms.") ]
879 string AGPSpecificationVersionConformance;
880 };
881
882
883 karl 1.1 // ===================================================================
884 // VideoControllerResolution
885 // ===================================================================
886 [Version ("2.6.0"), Description (
887 "VideoControllerResolution describes the various video modes "
888 "that a VideoController can support. Video modes are defined by "
889 "the possible horizontal and vertical resolutions, refresh "
890 "rate, scan mode and number of colors settings supported by a "
891 "Controller. The actual resolutions, etc. that are in use, are "
892 "the values specified in the VideoController object.") ]
893 class CIM_VideoControllerResolution : CIM_Setting {
894
895 [Override ("SettingID"), Key, MaxLen (256), Description (
896 "The inherited SettingID serves as part of the key for a "
897 "VideoControllerResolution instance.") ]
898 string SettingID;
899
900 [Description (
901 "Controller's horizontal resolution in Pixels."),
902 Units ("Pixels"),
903 ModelCorrespondence {
904 karl 1.1 "CIM_VideoController.CurrentHorizontalResolution"},
905 MappingStrings {"MIF.DMTF|Monitor Resolutions|002.2"} ]
906 uint32 HorizontalResolution;
907
908 [Description (
909 "Controller's vertical resolution in Pixels."),
910 Units ("Pixels"),
911 ModelCorrespondence {
912 "CIM_VideoController.CurrentVerticalResolution"},
913 MappingStrings {"MIF.DMTF|Monitor Resolutions|002.3"} ]
914 uint32 VerticalResolution;
915
916 [Description (
917 "Refresh rate in Hertz. If a range of rates is supported, use "
918 "the MinRefreshRate and MaxRefreshRate properties, and set "
919 "RefreshRate (this property) to 0."),
920 Units ("Hertz"),
921 ModelCorrespondence {"CIM_VideoController.CurrentRefreshRate"},
922 MappingStrings {"MIF.DMTF|Monitor Resolutions|002.4"} ]
923 uint32 RefreshRate;
924
925 karl 1.1 [Description (
926 "Minimum refresh rate in Hertz, when a range of rates is "
927 "supported at the specified resolutions."),
928 Units ("Hertz"),
929 ModelCorrespondence {"CIM_VideoController.MinRefreshRate"},
930 MappingStrings {"MIF.DMTF|Monitor Resolutions|002.6"} ]
931 uint32 MinRefreshRate;
932
933 [Description (
934 "Maximum refresh rate in Hertz, when a range of rates is "
935 "supported at the specified resolutions."),
936 Units ("Hertz"),
937 ModelCorrespondence {"CIM_VideoController.MaxRefreshRate"},
938 MappingStrings {"MIF.DMTF|Monitor Resolutions|002.7"} ]
939 uint32 MaxRefreshRate;
940
941 [Description (
942 "Integer indicating whether the Controller operates in "
943 "interlaced (value=5) or non-interlaced (4) mode."),
944 ValueMap {"1", "2", "3", "4", "5"},
945 Values {"Other", "Unknown", "Not Supported",
946 karl 1.1 "Non-Interlaced Operation", "Interlaced Operation"},
947 ModelCorrespondence {"CIM_VideoController.CurrentScanMode"},
948 MappingStrings {"MIF.DMTF|Monitor Resolutions|002.5"} ]
949 uint16 ScanMode;
950
951 [Description (
952 "Number of colors supported at the current resolutions."),
953 ModelCorrespondence {
954 "CIM_VideoController.CurrentNumberOfColors"} ]
955 uint64 NumberOfColors;
956 };
957
958
959 // ===================================================================
960 // VideoSetting
961 // ===================================================================
962 [Association, Version ("2.6.0"), Description (
963 "VideoSetting associates the VideoControllerResolution Setting "
964 "with the Controller(s) to which it applies.") ]
965 class CIM_VideoSetting : CIM_ElementSetting {
966
967 karl 1.1 [Override ("Element"), Description (
968 "The VideoController.") ]
969 CIM_VideoController REF Element;
970
971 [Override ("Setting"), Description (
972 "The resolutions, refresh rates, scan mode and number of "
973 "colors that can be set for the Controller.") ]
974 CIM_VideoControllerResolution REF Setting;
975 };
976
977
978 // ===================================================================
979 // PCIController
980 // ===================================================================
981 [Version ("2.6.0"), Description (
982 "PCIController is a superclass for the PCIBridge and PCIDevice "
983 "classes. These classes model adapters and bridges on a PCI "
984 "bus. The properties in PCIController and its subclasses are "
985 "defined in the various PCI Specifications published by the "
986 "PCI SIG.") ]
987 class CIM_PCIController : CIM_Controller {
988 karl 1.1
989 [Description (
990 "Current contents of the register that provides basic "
991 "control over the device's ability to respond "
992 "to, and/or perform PCI accesses.") ]
993 uint16 CommandRegister;
994
995 [Description (
996 "An array of integers indicating controller capabilities. "
997 "Information such as \"Supports 66MHz\" (value=2) is "
998 "specified in this property. The data in the Capabilities "
999 "array is gathered from the PCI Status Register and the PCI "
1000 "Capabilities List as defined in the PCI Specification."),
1001 ArrayType ("Indexed"),
1002 ValueMap {"0", "1", "2", "3", "4", "5", "6", "7", "8", "9",
1003 "10", "11", "12"},
1004 Values {"Unknown", "Other", "Supports 66MHz",
1005 "Supports User Definable Features",
1006 "Supports Fast Back-to-Back Transactions",
1007 "PCI-X Capable", "PCI Power Management Supported",
1008 "Message Signaled Interrupts Supported",
1009 karl 1.1 "Parity Error Recovery Capable",
1010 "AGP Supported",
1011 // 10
1012 "Vital Product Data Supported",
1013 "Provides Slot Identification", "Hot Swap Supported"},
1014 ModelCorrespondence {
1015 "CIM_PCIController.CapabilityDescriptions"} ]
1016 uint16 Capabilities[];
1017
1018 [Description (
1019 "An array of free-form strings providing more detailed "
1020 "explanations for any of the PCIController features indicated "
1021 "in the Capabilities array. Note, each entry of this array "
1022 "is related to the entry in the Capabilities array that "
1023 "is located at the same index."),
1024 ArrayType ("Indexed"),
1025 ModelCorrespondence {"CIM_PCIController.Capabilities"} ]
1026 string CapabilityDescriptions[];
1027
1028 [Description (
1029 "The slowest device select timing for a target device."),
1030 karl 1.1 ValueMap {"0", "1", "2", "3", "4", "5"},
1031 Values {"Unknown", "Other", "Fast", "Medium", "Slow",
1032 "Reserved"} ]
1033 uint16 DeviceSelectTiming;
1034
1035 [Description (
1036 "Register of 8 bits that identifies the basic function of the "
1037 "PCI device. This is only the upper byte (offset 0Bh) of the "
1038 "3 byte ClassCode field. Note that the property's ValueMap "
1039 "array specifies the decimal representation of this "
1040 "information."),
1041 ValueMap {"0", "1", "2", "3", "4", "5", "6", "7", "8", "9",
1042 "10", "11", "12", "13", "14", "15", "16", "17",
1043 "18..254", "255"},
1044 Values {"Pre 2.0", "Mass Storage", "Network", "Display",
1045 "Multimedia", "Memory", "Bridge", "Simple Communications",
1046 "Base Peripheral", "Input",
1047 // 10
1048 "Docking Station", "Processor",
1049 "Serial Bus", "Wireless", "Intelligent I/O",
1050 "Satellite Communication", "Encryption/Decryption",
1051 karl 1.1 "Data Acquisition and Signal Processing",
1052 // 18 - 255
1053 "PCI Reserved", "Other"} ]
1054 uint8 ClassCode;
1055
1056 [Description (
1057 "Specifies the system cache line size in doubleword increments "
1058 "(e.g., a 486-based system would store the value 04h, "
1059 "indicating a cache line size of four doublewords)."),
1060 Units ("DoubleWords") ]
1061 uint8 CacheLineSize;
1062
1063 [Description (
1064 "Defines the minimum amount of time, in PCI clock cycles, that "
1065 "the bus master can retain ownership of the bus."),
1066 Units ("PCI clock cycles") ]
1067 uint8 LatencyTimer;
1068
1069 [Description (
1070 "Defines the PCI interrupt request pin (INTA# to "
1071 "INTD#) to which a PCI functional device is connected."),
1072 karl 1.1 ValueMap {"0", "1", "2", "3", "4", "5"},
1073 Values {"None", "INTA#", "INTB#", "INTC#", "INTD#", "Unknown"} ]
1074 uint16 InterruptPin;
1075
1076 [Description (
1077 "Doubleword Expansion ROM base memory address."),
1078 Units ("DoubleWords") ]
1079 uint32 ExpansionROMBaseAddress;
1080
1081 [Description (
1082 "Reports if the PCI device can perform the self test "
1083 "function. Returns bit 7 of the BIST register as a boolean.") ]
1084 boolean SelfTestEnabled;
1085
1086 [Description (
1087 "Method to invoke PCI device self-test. This method sets bit "
1088 "6 of the BIST register. The return result is the lower "
1089 "four bits of the BIST register where 0 indicates success and "
1090 "non-zero is a device dependent failure. Support for this "
1091 "method is optional in the PCI Specification.") ]
1092 uint8 BISTExecution( );
1093 karl 1.1 };
1094
1095
1096 // ===================================================================
1097 // PCIDevice
1098 // ===================================================================
1099 [Version ("2.6.0"), Description (
1100 "Capabilities and management of a PCI device controller "
1101 "on an adapter card.") ]
1102 class CIM_PCIDevice : CIM_PCIController {
1103
1104 [Description ("Array of doubleword base memory addresses.") ]
1105 uint32 BaseAddress[6];
1106
1107 [Description ("Subsystem identifier code.") ]
1108 uint16 SubsystemID;
1109
1110 [Description (
1111 "Subsystem vendor ID. ID information is reported from a "
1112 "PCIDevice via protocol-specific requests. The correct place "
1113 "in the CIM Schema for this information is in CIM_Physical"
1114 karl 1.1 "Element (the Manufacturer property) for hardware, and "
1115 "CIM_Product (the Vendor property) if the information is "
1116 "related to Product acquisition. This data is also reported "
1117 "here since it is part of the standard output from the "
1118 "Device, and as an optimization.") ]
1119 uint16 SubsystemVendorID;
1120
1121 [Description (
1122 "Register indiating how long the master would like to "
1123 "retain PCI bus ownership whenever it initiates a "
1124 "transaction. A zero value indicates no requirement."),
1125 Units ("250 nanoseconds") ]
1126 uint8 MinGrantTime;
1127
1128 [Description (
1129 "Register specifying how often the device needs access to "
1130 "the PCI bus in 250ns. A zero value indicates no "
1131 "requirement."),
1132 Units ("250 nanoseconds") ]
1133 uint8 MaxLatency;
1134 };
1135 karl 1.1
1136
1137 // ===================================================================
1138 // PCIBridge
1139 // ===================================================================
1140 [Version ("2.6.0"), Description (
1141 "Capabilities and management of a PCI controller providing "
1142 "bridge to bridge capability.") ]
1143 class CIM_PCIBridge : CIM_PCIController {
1144
1145 [Description ("Array of doubleword base memory addresses.") ]
1146 uint32 BaseAddress[2];
1147
1148 [Description (
1149 "The type of bridge. Except for \"Host\" (value=0), the type "
1150 "of bridge is PCI to <value>. For type \"Host\", the device is "
1151 "a Host to PCI bridge."),
1152 ValueMap {"0", "1", "2", "3", "4", "5", "6", "7", "8",
1153 "128"},
1154 Values {"Host", "ISA", "EISA", "Micro Channel", "PCI",
1155 "PCMCIA", "NuBus", "CardBus", "RACEway",
1156 karl 1.1 // 128
1157 "Other"} ]
1158 uint16 BridgeType;
1159
1160 [Description (
1161 "The timeslice for the secondary interface when the bridge "
1162 "is acting as an initiator. A zero value indicates no "
1163 "requirement."),
1164 Units ("PCI clock cycles") ]
1165 uint8 SecondaryLatencyTimer;
1166
1167 [Description (
1168 "The number of the highest numbered bus that exists behind "
1169 "the bridge.") ]
1170 uint8 SubordinateBusNumber;
1171
1172 [Description (
1173 "The number of the PCI bus segment to which the secondary "
1174 "interface of the bridge is connected.") ]
1175 uint8 SecondayBusNumber;
1176
1177 karl 1.1 [Description (
1178 "The number of the PCI bus segment to which the primary "
1179 "interface of the bridge is connected.") ]
1180 uint8 PrimaryBusNumber;
1181
1182 [Description (
1183 "The contents of the Bridge's SecondaryStatusRegister. "
1184 "For more information on the contents of this register, refer "
1185 "to the PCI-to-PCI Bridge Architecture Specification.") ]
1186 uint16 SecondaryStatusRegister;
1187
1188 [Description (
1189 "The slowest device select timing for a target device on the "
1190 "secondary bus."),
1191 ValueMap {"0", "1", "2", "3", "4", "5"},
1192 Values {"Unknown", "Other", "Fast", "Medium", "Slow",
1193 "Reserved"} ]
1194 uint16 SecondaryBusDeviceSelectTiming;
1195
1196 [Description (
1197 "End address of the I/O addresses supported by the bus. The "
1198 karl 1.1 "upper four bits of this property specify the address bits, "
1199 "AD[15::12], of the I/O address. The remaining 12 bits of "
1200 "the I/O address are assumed to be all 1's.") ]
1201 uint8 IOLimit;
1202
1203 [Description (
1204 "Base address of I/O addresses supported by the bus. The "
1205 "upper four bits of this property specify the address bits, "
1206 "AD[15::12], of the I/O address. The remaining 12 bits of "
1207 "the I/O address are assumed to be 0.") ]
1208 uint8 IOBase;
1209
1210 [Description (
1211 "End address of the memory supported by the bus. The "
1212 "upper twelve bits of this property specify the address bits, "
1213 "AD[31::20], of a 32-bit memory address. The remaining 20 "
1214 "bits of the address are assumed to be all 1's.") ]
1215 uint16 MemoryLimit;
1216
1217 [Description (
1218 "Base address of the memory supported by the bus. The "
1219 karl 1.1 "upper twelve bits of this property specify the address bits, "
1220 "AD[31::20], of a 32-bit memory address. The remaining 20 "
1221 "bits of the address are assumed to be 0.") ]
1222 uint16 MemoryBase;
1223
1224 [Description (
1225 "End address of the memory that can be prefetched by the bus. "
1226 "The upper twelve bits of this property specify the address "
1227 "bits, AD[31::20], of a 32-bit memory address. The remaining "
1228 "20 bits of the address are assumed to be all 1's.") ]
1229 uint16 PrefetchMemoryLimit;
1230
1231 [Description (
1232 "Base address of the memory that can be prefetched by the bus. "
1233 "The upper twelve bits of this property specify the address "
1234 "bits, AD[31::20], of a 32-bit memory address. The remaining "
1235 "20 bits of the address are assumed to be 0.") ]
1236 uint16 PrefetchMemoryBase;
1237
1238 [Description (
1239 "Upper 32 bits of the supported prefetch end address when "
1240 karl 1.1 "64-bit addressing is used. The lower 32 bits are assumed to "
1241 "be all 1's.") ]
1242 uint32 PrefetchLimitUpper32;
1243
1244 [Description (
1245 "Upper 32 bits of the supported prefetch base address when "
1246 "64-bit addressing is used. The lower 32 bits are assumed "
1247 "to be 0.") ]
1248 uint32 PrefetchBaseUpper32;
1249
1250 [Description (
1251 "Upper 16 bits of the supported I/O end address when 32-bit "
1252 "I/O addressing is used. The lower 16 bits are assumed to be "
1253 "all 1's.") ]
1254 uint16 IOLimitUpper16;
1255
1256 [Description (
1257 "Upper 16 bits of the supported I/O base address when 32-bit "
1258 "I/O addressing is used. The lower 16 bits are assumed to be "
1259 "0.") ]
1260 uint16 IOBaseUpper16;
1261 karl 1.1 };
1262
1263
1264 // ===================================================================
1265 // end of file
1266 // ===================================================================
|
Return to
Device27_Controller.mof
CVS log
Up to [Pegasus] / pegasus / Schemas / CIMPrelim271