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File: [Pegasus] / pegasus / Schemas / CIM231 / DMTF / Device / CIM_ProcessorCore.mof
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Revision: 1.1, Tue Jan 24 13:50:08 2012 UTC (12 years, 5 months ago) by marek Branch: MAIN CVS Tags: preBug9676, postBug9676, TASK-TASK_PEP362_RestfulService_branch-root, TASK-TASK_PEP362_RestfulService_branch-merged_out_from_trunk, TASK-TASK_PEP362_RestfulService_branch-merged_in_to_trunk, TASK-TASK_PEP362_RestfulService_branch-merged_in_from_branch, TASK-TASK_PEP362_RestfulService_branch-branch, TASK-PEP362_RestfulService-root, TASK-PEP362_RestfulService-merged_out_to_branch, TASK-PEP362_RestfulService-merged_out_from_trunk, TASK-PEP362_RestfulService-merged_in_to_trunk, TASK-PEP362_RestfulService-merged_in_from_branch, TASK-PEP362_RestfulService-branch, TASK-PEP317_pullop-merged_out_from_trunk, TASK-PEP317_pullop-merged_in_to_trunk, RELEASE_2_14_1, RELEASE_2_14_0-RC2, RELEASE_2_14_0-RC1, RELEASE_2_14_0, RELEASE_2_14-root, RELEASE_2_14-branch, RELEASE_2_13_0-RC2, RELEASE_2_13_0-RC1, RELEASE_2_13_0-FC, RELEASE_2_13_0, RELEASE_2_13-root, RELEASE_2_13-branch, RELEASE_2_12_1-RC1, RELEASE_2_12_1, RELEASE_2_12_0-RC1, RELEASE_2_12_0-FC, RELEASE_2_12_0, RELEASE_2_12-root, RELEASE_2_12-branch, HEAD, CIMRS_WORK_20130824 Branch point for: TASK-PEP317_pullop-branch BUG#:9155 TITLE: Upgrade Pegasus to Include the CIM 2.31 Schema in CVS DESCRIPTION: |
// Copyright (c) 2009 DMTF. All rights reserved. [Version ( "2.22.0" ), UMLPackagePath ( "CIM::Device::Processor" ), Description ( "The CIM_ProcessorCore class inherits from " "CIM_EnabledLogicalElement and describes a specific processor " "core. CIM_ProcessorCore instances are related to the instance " "of CIM_Processor that represents the processor they are " "contained in." )] class CIM_ProcessorCore : CIM_EnabledLogicalElement { [Key, Override ( "InstanceID" ), Description ( "Within the scope of the instantiating Namespace, " "InstanceID opaquely and uniquely identifies an instance " "of this class. \n" "In order to ensure uniqueness within the NameSpace, the " "value of InstanceID SHOULD be constructed using the " "following \'preferred\' algorithm: \n" "<OrgID>:<LocalID> \n" "Where <OrgID> and <LocalID> are separated by a colon " "\':\', and where <OrgID> MUST include a copyrighted, " "trademarked or otherwise unique name that is owned by " "the business entity creating/defining the InstanceID, or " "is a registered ID that is assigned to the business " "entity by a recognized global authority (This is similar " "to the <Schema Name>_<Class Name> structure of Schema " "class names.) In addition, to ensure uniqueness <OrgID> " "MUST NOT contain a colon (\':\'). When using this " "algorithm, the first colon to appear in InstanceID MUST " "appear between <OrgID> and <LocalID>. \n" "<LocalID> is chosen by the business entity and SHOULD " "not be re-used to identify different underlying " "(real-world) elements. If the above \'preferred\' " "algorithm is not used, the defining entity MUST assure " "that the resultant InstanceID is not re-used across any " "InstanceIDs produced by this or other providers for this " "instance\'s NameSpace. \n" "For DMTF defined instances, the \'preferred\' algorithm " "MUST be used with the <OrgID> set to \'CIM\'." )] string InstanceID; [Description ( "The CoreEnabledState property is the configuration state " "of the processor core. For example, the core might be " "disabled by the user (value=2), or disabled due to a " "POST error (value=3)." ), ValueMap { "0", "1", "2", "3", "4", "5" }, Values { "Unknown", "DMTF Reserved", "Core Enabled", "Core Disabled", "Core Disabled by User", "Core Disabled By POST Error)" }] uint16 CoreEnabledState; [Description ( "Loading of this processor core, averaged over the last " "minute, in Percent." ), Units ( "Percent" ), Gauge, PUnit ( "percent" )] uint16 LoadPercentage; };
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