version 1.1.2.1, 2012/01/24 13:50:08
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version 1.1.2.2, 2012/02/15 17:46:22
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// Copyright (c) 2011 DMTF. All rights reserved. |
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[Version ( "2.28.0" ), |
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UMLPackagePath ( "CIM::Device::Controller" ), |
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Description ( |
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"PCIController is a superclass for the PCIBridge and PCIDevice " |
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"classes. These classes model adapters and bridges on a PCI " |
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"bus. The properties in PCIController and its subclasses are " |
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"defined in the various PCI Specifications that are published " |
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"by the PCI SIG." )] |
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class CIM_PCIController : CIM_Controller { |
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[Description ( |
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"Current contents of the register that provides basic " |
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"control over the ability of the device to respond to or " |
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"perform PCI accesses." )] |
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uint16 CommandRegister; |
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[Description ( |
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"An array of integers that indicates controller " |
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"capabilities. Information such as \"Supports 66MHz\" " |
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"(value=2) is specified in this property. The data in the " |
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"Capabilities array is gathered from the PCI Status " |
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"Register and the PCI Capabilities List as defined in the " |
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"PCI Specification." ), |
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ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", |
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"10", "11", "12", "13", "14", "15", "16..32767", |
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"32768..65535" }, |
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Values { "Unknown", "Other", "Supports 66MHz", |
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"Supports User Definable Features", |
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"Supports Fast Back-to-Back Transactions", |
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"PCI-X Capable", "PCI Power Management Supported", |
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"Message Signaled Interrupts Supported", |
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"Parity Error Recovery Capable", "AGP Supported", |
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"Vital Product Data Supported", |
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"Provides Slot Identification", "Hot Swap Supported", |
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"Supports PCIe", "Supports PCIe Gen 2", |
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"Supports PCIe Gen 3", "DMTF Reserved", "Vendor Reserved" }, |
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ArrayType ( "Indexed" ), |
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ModelCorrespondence { |
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"CIM_PCIController.CapabilityDescriptions" }] |
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uint16 Capabilities[]; |
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[Description ( |
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"An array of free-form strings that provides more " |
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"detailed explanations for any of the PCIController " |
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"features that are indicated in the Capabilities array. " |
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"Note, each entry of this array is related to the entry " |
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"in the Capabilities array that is located at the same " |
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"index." ), |
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ArrayType ( "Indexed" ), |
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ModelCorrespondence { "CIM_PCIController.Capabilities" }] |
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string CapabilityDescriptions[]; |
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[Description ( |
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"The slowest device-select timing for a target device." ), |
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ValueMap { "0", "1", "2", "3", "4", "5" }, |
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Values { "Unknown", "Other", "Fast", "Medium", "Slow", |
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"Reserved" }] |
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uint16 DeviceSelectTiming; |
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[Description ( |
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"Register of 8 bits that identifies the basic function of " |
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"the PCI device. This property is only the upper byte " |
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"(offset 0Bh) of the 3-byte ClassCode field. Note that " |
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"the ValueMap array of the property specifies the decimal " |
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"representation of this information." ), |
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ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", |
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"10", "11", "12", "13", "14", "15", "16", "17", "18..254", |
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"255" }, |
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Values { "Pre 2.0", "Mass Storage", "Network", "Display", |
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"Multimedia", "Memory", "Bridge", "Simple Communications", |
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"Base Peripheral", "Input", "Docking Station", |
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"Processor", "Serial Bus", "Wireless", "Intelligent I/O", |
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"Satellite Communication", "Encryption/Decryption", |
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"Data Acquisition and Signal Processing", "PCI Reserved", |
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"Other" }] |
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uint8 ClassCode; |
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[Description ( |
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"Specifies the system cache line size in doubleword " |
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"increments (for example, a 486-based system would store " |
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"the value 04h, indicating a cache line size of four " |
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"doublewords." ), |
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Units ( "DoubleWords" ), |
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PUnit ( "dataword * 2" )] |
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uint8 CacheLineSize; |
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[Description ( |
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"Defines the minimum amount of time, in PCI clock cycles, " |
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"that the bus master can retain ownership of the bus." ), |
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Units ( "PCI clock cycles" ), |
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PUnit ( "cycle" )] |
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uint8 LatencyTimer; |
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[Description ( |
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"Defines the PCI interrupt request pin (INTA# to INTD#) " |
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"to which a PCI functional device is connected." ), |
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ValueMap { "0", "1", "2", "3", "4", "5" }, |
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Values { "None", "INTA#", "INTB#", "INTC#", "INTD#", "Unknown" }] |
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uint16 InterruptPin; |
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[Description ( "Doubleword Expansion ROM-base memory address." ), |
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Units ( "DoubleWords" ), |
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PUnit ( "dataword * 2" )] |
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uint32 ExpansionROMBaseAddress; |
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[Description ( |
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"Reports if the PCI device can perform the self-test " |
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"function. Returns bit 7 of the BIST register as a " |
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"Boolean." )] |
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boolean SelfTestEnabled; |
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[Description ( |
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"Method to invoke PCI device self-test. This method sets " |
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"bit 6 of the BIST register. The return result is the " |
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"lower 4 bits of the BIST register where 0 indicates " |
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"success and non-zero is a device-dependent failure. " |
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"Support for this method is optional in the PCI " |
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"Specification." )] |
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uint8 BISTExecution( |
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); |
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}; |