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File: [Pegasus] / pegasus / Schemas / CIM231 / DMTF / Device / CIM_PCIBridge.mof
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Revision: 1.1, Tue Jan 24 13:50:08 2012 UTC (12 years, 5 months ago) by marek Branch: MAIN CVS Tags: preBug9676, postBug9676, TASK-TASK_PEP362_RestfulService_branch-root, TASK-TASK_PEP362_RestfulService_branch-merged_out_from_trunk, TASK-TASK_PEP362_RestfulService_branch-merged_in_to_trunk, TASK-TASK_PEP362_RestfulService_branch-merged_in_from_branch, TASK-TASK_PEP362_RestfulService_branch-branch, TASK-PEP362_RestfulService-root, TASK-PEP362_RestfulService-merged_out_to_branch, TASK-PEP362_RestfulService-merged_out_from_trunk, TASK-PEP362_RestfulService-merged_in_to_trunk, TASK-PEP362_RestfulService-merged_in_from_branch, TASK-PEP362_RestfulService-branch, TASK-PEP317_pullop-merged_out_from_trunk, TASK-PEP317_pullop-merged_in_to_trunk, RELEASE_2_14_1, RELEASE_2_14_0-RC2, RELEASE_2_14_0-RC1, RELEASE_2_14_0, RELEASE_2_14-root, RELEASE_2_14-branch, RELEASE_2_13_0-RC2, RELEASE_2_13_0-RC1, RELEASE_2_13_0-FC, RELEASE_2_13_0, RELEASE_2_13-root, RELEASE_2_13-branch, RELEASE_2_12_1-RC1, RELEASE_2_12_1, RELEASE_2_12_0-RC1, RELEASE_2_12_0-FC, RELEASE_2_12_0, RELEASE_2_12-root, RELEASE_2_12-branch, HEAD, CIMRS_WORK_20130824 Branch point for: TASK-PEP317_pullop-branch BUG#:9155 TITLE: Upgrade Pegasus to Include the CIM 2.31 Schema in CVS DESCRIPTION: |
// Copyright (c) 2009 DMTF. All rights reserved. [Version ( "2.22.0" ), UMLPackagePath ( "CIM::Device::Controller" ), Description ( "Capabilities and management of a PCI controller that provide " "bridge-to-bridge capability." )] class CIM_PCIBridge : CIM_PCIDevice { [Description ( "The type of bridge. Except for \"Host\" (value=0) and " "\"PCIe-to-PCI\" (value=10), the type of bridge is " "PCI-to-<value>. For type \"Host\", the device is a " "Host-to-PCI bridge. For type \"PCIe-to-PCI\", the device " "is a PCI Express-to-PCI bridge." ), ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "128", ".." }, Values { "Host", "ISA", "EISA", "Micro Channel", "PCI", "PCMCIA", "NuBus", "CardBus", "RACEway", "AGP", "PCIe", "PCIe-to-PCI", // 128 "Other", "DMTF Reserved" }] uint16 BridgeType; [Description ( "The timeslice for the secondary interface when the " "bridge is acting as an initiator. A 0 value indicates no " "requirement." ), Units ( "PCI clock cycles" ), PUnit ( "cycle" )] uint8 SecondaryLatencyTimer; [Description ( "The number of the highest numbered bus that exists " "behind the bridge." )] uint8 SubordinateBusNumber; [Description ( "The number of the PCI bus segment to which the secondary " "interface of the bridge is connected." )] uint8 SecondayBusNumber; [Description ( "The number of the PCI bus segment to which the primary " "interface of the bridge is connected." )] uint8 PrimaryBusNumber; [Description ( "The contents of the SecondaryStatusRegister of the " "Bridge. For more information on the contents of this " "register, refer to the PCI-to-PCI Bridge Architecture " "Specification." )] uint16 SecondaryStatusRegister; [Description ( "The slowest device-select timing for a target device on " "the secondary bus." ), ValueMap { "0", "1", "2", "3", "4", "5" }, Values { "Unknown", "Other", "Fast", "Medium", "Slow", "DMTF Reserved" }] uint16 SecondaryBusDeviceSelectTiming; [Description ( "End address of the I/O addresses supported by the bus. " "The upper 4 bits of this property specify the address " "bits, AD[15::12], of the I/O address. Each of the " "remaining 12 bits of the I/O address are assumed to be " "1." )] uint8 IOLimit; [Description ( "Base address of I/O addresses supported by the bus. The " "upper 4 bits of this property specify the address bits, " "AD[15::12], of the I/O address. Each of the remaining 12 " "bits of the I/O address are assumed to be 0." )] uint8 IOBase; [Description ( "End address of the memory supported by the bus. The " "upper 12 bits of this property specify the address bits, " "AD[31::20], of a 32-bit memory address. Each of the " "remaining 20 bits of the address are assumed to be 1." )] uint16 MemoryLimit; [Description ( "Base address of the memory supported by the bus. The " "upper 12 bits of this property specify the address bits, " "AD[31::20], of a 32-bit memory address. Each of the " "remaining 20 bits of the address are assumed to be 0." )] uint16 MemoryBase; [Description ( "End address of the memory that can be prefetched by the " "bus. The upper 12 bits of this property specify the " "address bits, AD[31::20], of a 32-bit memory address. " "Each of the remaining 20 bits of the address are assumed " "to be 1." )] uint16 PrefetchMemoryLimit; [Description ( "Base address of the memory that can be prefetched by the " "bus. The upper 12 bits of this property specify the " "address bits, AD[31::20], of a 32-bit memory address. " "Each of the remaining 20 bits of the address are assumed " "to be 0." )] uint16 PrefetchMemoryBase; [Description ( "Upper 32 bits of the supported prefetch end address when " "64-bit addressing is used. The lower 32 bits are each " "assumed to be 1." )] uint32 PrefetchLimitUpper32; [Description ( "Upper 32 bits of the supported prefetch base address " "when 64-bit addressing is used. The lower 32 bits are " "assumed to be 0." )] uint32 PrefetchBaseUpper32; [Description ( "Upper 16 bits of the supported I/O end address when " "32-bit I/O addressing is used. The lower 16 bits are " "each assumed to be 1." )] uint16 IOLimitUpper16; [Description ( "Upper 16 bits of the supported I/O base address when " "32-bit I/O addressing is used. The lower 16 bits are " "assumed to be 0." )] uint16 IOBaseUpper16; };
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