1 marek 1.1 // Copyright (c) 2009 DMTF.  All rights reserved.
  2              [Version ( "2.22.0" ), 
  3               UMLPackagePath ( "CIM::Device::Controller" ), 
  4               Description ( 
  5                  "Capabilities and management of a PCI controller that provide "
  6                  "bridge-to-bridge capability." )]
  7           class CIM_PCIBridge : CIM_PCIDevice {
  8           
  9                 [Description ( 
 10                     "The type of bridge. Except for \"Host\" (value=0) and "
 11                     "\"PCIe-to-PCI\" (value=10), the type of bridge is "
 12                     "PCI-to-<value>. For type \"Host\", the device is a "
 13                     "Host-to-PCI bridge. For type \"PCIe-to-PCI\", the device "
 14                     "is a PCI Express-to-PCI bridge." ), 
 15                  ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", 
 16                     "10", "11", "128", ".." }, 
 17                  Values { "Host", "ISA", "EISA", "Micro Channel", "PCI", 
 18                     "PCMCIA", "NuBus", "CardBus", "RACEway", "AGP", "PCIe", 
 19                     "PCIe-to-PCI", // 128 
 20                     "Other", "DMTF Reserved" }]
 21              uint16 BridgeType;
 22 marek 1.1 
 23                 [Description ( 
 24                     "The timeslice for the secondary interface when the "
 25                     "bridge is acting as an initiator. A 0 value indicates no "
 26                     "requirement." ), 
 27                  Units ( "PCI clock cycles" ), 
 28                  PUnit ( "cycle" )]
 29              uint8 SecondaryLatencyTimer;
 30           
 31                 [Description ( 
 32                     "The number of the highest numbered bus that exists "
 33                     "behind the bridge." )]
 34              uint8 SubordinateBusNumber;
 35           
 36                 [Description ( 
 37                     "The number of the PCI bus segment to which the secondary "
 38                     "interface of the bridge is connected." )]
 39              uint8 SecondayBusNumber;
 40           
 41                 [Description ( 
 42                     "The number of the PCI bus segment to which the primary "
 43 marek 1.1           "interface of the bridge is connected." )]
 44              uint8 PrimaryBusNumber;
 45           
 46                 [Description ( 
 47                     "The contents of the SecondaryStatusRegister of the "
 48                     "Bridge. For more information on the contents of this "
 49                     "register, refer to the PCI-to-PCI Bridge Architecture "
 50                     "Specification." )]
 51              uint16 SecondaryStatusRegister;
 52           
 53                 [Description ( 
 54                     "The slowest device-select timing for a target device on "
 55                     "the secondary bus." ), 
 56                  ValueMap { "0", "1", "2", "3", "4", "5" }, 
 57                  Values { "Unknown", "Other", "Fast", "Medium", "Slow", 
 58                     "DMTF Reserved" }]
 59              uint16 SecondaryBusDeviceSelectTiming;
 60           
 61                 [Description ( 
 62                     "End address of the I/O addresses supported by the bus. "
 63                     "The upper 4 bits of this property specify the address "
 64 marek 1.1           "bits, AD[15::12], of the I/O address. Each of the "
 65                     "remaining 12 bits of the I/O address are assumed to be "
 66                     "1." )]
 67              uint8 IOLimit;
 68           
 69                 [Description ( 
 70                     "Base address of I/O addresses supported by the bus. The "
 71                     "upper 4 bits of this property specify the address bits, "
 72                     "AD[15::12], of the I/O address. Each of the remaining 12 "
 73                     "bits of the I/O address are assumed to be 0." )]
 74              uint8 IOBase;
 75           
 76                 [Description ( 
 77                     "End address of the memory supported by the bus. The "
 78                     "upper 12 bits of this property specify the address bits, "
 79                     "AD[31::20], of a 32-bit memory address. Each of the "
 80                     "remaining 20 bits of the address are assumed to be 1." )]
 81              uint16 MemoryLimit;
 82           
 83                 [Description ( 
 84                     "Base address of the memory supported by the bus. The "
 85 marek 1.1           "upper 12 bits of this property specify the address bits, "
 86                     "AD[31::20], of a 32-bit memory address. Each of the "
 87                     "remaining 20 bits of the address are assumed to be 0." )]
 88              uint16 MemoryBase;
 89           
 90                 [Description ( 
 91                     "End address of the memory that can be prefetched by the "
 92                     "bus. The upper 12 bits of this property specify the "
 93                     "address bits, AD[31::20], of a 32-bit memory address. "
 94                     "Each of the remaining 20 bits of the address are assumed "
 95                     "to be 1." )]
 96              uint16 PrefetchMemoryLimit;
 97           
 98                 [Description ( 
 99                     "Base address of the memory that can be prefetched by the "
100                     "bus. The upper 12 bits of this property specify the "
101                     "address bits, AD[31::20], of a 32-bit memory address. "
102                     "Each of the remaining 20 bits of the address are assumed "
103                     "to be 0." )]
104              uint16 PrefetchMemoryBase;
105           
106 marek 1.1       [Description ( 
107                     "Upper 32 bits of the supported prefetch end address when "
108                     "64-bit addressing is used. The lower 32 bits are each "
109                     "assumed to be 1." )]
110              uint32 PrefetchLimitUpper32;
111           
112                 [Description ( 
113                     "Upper 32 bits of the supported prefetch base address "
114                     "when 64-bit addressing is used. The lower 32 bits are "
115                     "assumed to be 0." )]
116              uint32 PrefetchBaseUpper32;
117           
118                 [Description ( 
119                     "Upper 16 bits of the supported I/O end address when "
120                     "32-bit I/O addressing is used. The lower 16 bits are "
121                     "each assumed to be 1." )]
122              uint16 IOLimitUpper16;
123           
124                 [Description ( 
125                     "Upper 16 bits of the supported I/O base address when "
126                     "32-bit I/O addressing is used. The lower 16 bits are "
127 marek 1.1           "assumed to be 0." )]
128              uint16 IOBaseUpper16;
129           
130           
131           };