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version 1.1.2.1, 2012/01/24 13:50:08
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version 1.1.2.2, 2012/02/15 17:46:22
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// Copyright (c) 2009 DMTF. All rights reserved. |
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[Version ( "2.22.0" ), |
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UMLPackagePath ( "CIM::Device::Controller" ), |
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Description ( |
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"Capabilities and management of a PCI controller that provide " |
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"bridge-to-bridge capability." )] |
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class CIM_PCIBridge : CIM_PCIDevice { |
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|
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[Description ( |
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"The type of bridge. Except for \"Host\" (value=0) and " |
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"\"PCIe-to-PCI\" (value=10), the type of bridge is " |
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"PCI-to-<value>. For type \"Host\", the device is a " |
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"Host-to-PCI bridge. For type \"PCIe-to-PCI\", the device " |
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"is a PCI Express-to-PCI bridge." ), |
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ValueMap { "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", |
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"10", "11", "128", ".." }, |
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Values { "Host", "ISA", "EISA", "Micro Channel", "PCI", |
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"PCMCIA", "NuBus", "CardBus", "RACEway", "AGP", "PCIe", |
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"PCIe-to-PCI", // 128 |
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"Other", "DMTF Reserved" }] |
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uint16 BridgeType; |
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|
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[Description ( |
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"The timeslice for the secondary interface when the " |
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"bridge is acting as an initiator. A 0 value indicates no " |
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"requirement." ), |
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Units ( "PCI clock cycles" ), |
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PUnit ( "cycle" )] |
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uint8 SecondaryLatencyTimer; |
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|
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[Description ( |
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"The number of the highest numbered bus that exists " |
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"behind the bridge." )] |
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uint8 SubordinateBusNumber; |
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|
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[Description ( |
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"The number of the PCI bus segment to which the secondary " |
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"interface of the bridge is connected." )] |
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uint8 SecondayBusNumber; |
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|
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[Description ( |
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"The number of the PCI bus segment to which the primary " |
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"interface of the bridge is connected." )] |
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uint8 PrimaryBusNumber; |
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|
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[Description ( |
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"The contents of the SecondaryStatusRegister of the " |
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"Bridge. For more information on the contents of this " |
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"register, refer to the PCI-to-PCI Bridge Architecture " |
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"Specification." )] |
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uint16 SecondaryStatusRegister; |
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|
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[Description ( |
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"The slowest device-select timing for a target device on " |
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"the secondary bus." ), |
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ValueMap { "0", "1", "2", "3", "4", "5" }, |
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Values { "Unknown", "Other", "Fast", "Medium", "Slow", |
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"DMTF Reserved" }] |
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uint16 SecondaryBusDeviceSelectTiming; |
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|
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[Description ( |
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"End address of the I/O addresses supported by the bus. " |
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"The upper 4 bits of this property specify the address " |
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"bits, AD[15::12], of the I/O address. Each of the " |
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"remaining 12 bits of the I/O address are assumed to be " |
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"1." )] |
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uint8 IOLimit; |
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|
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[Description ( |
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"Base address of I/O addresses supported by the bus. The " |
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"upper 4 bits of this property specify the address bits, " |
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"AD[15::12], of the I/O address. Each of the remaining 12 " |
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"bits of the I/O address are assumed to be 0." )] |
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uint8 IOBase; |
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|
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[Description ( |
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"End address of the memory supported by the bus. The " |
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"upper 12 bits of this property specify the address bits, " |
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"AD[31::20], of a 32-bit memory address. Each of the " |
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"remaining 20 bits of the address are assumed to be 1." )] |
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uint16 MemoryLimit; |
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|
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[Description ( |
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"Base address of the memory supported by the bus. The " |
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"upper 12 bits of this property specify the address bits, " |
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"AD[31::20], of a 32-bit memory address. Each of the " |
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"remaining 20 bits of the address are assumed to be 0." )] |
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uint16 MemoryBase; |
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|
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[Description ( |
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"End address of the memory that can be prefetched by the " |
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"bus. The upper 12 bits of this property specify the " |
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"address bits, AD[31::20], of a 32-bit memory address. " |
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"Each of the remaining 20 bits of the address are assumed " |
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"to be 1." )] |
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uint16 PrefetchMemoryLimit; |
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|
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[Description ( |
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"Base address of the memory that can be prefetched by the " |
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"bus. The upper 12 bits of this property specify the " |
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"address bits, AD[31::20], of a 32-bit memory address. " |
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"Each of the remaining 20 bits of the address are assumed " |
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"to be 0." )] |
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uint16 PrefetchMemoryBase; |
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|
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[Description ( |
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"Upper 32 bits of the supported prefetch end address when " |
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"64-bit addressing is used. The lower 32 bits are each " |
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"assumed to be 1." )] |
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uint32 PrefetchLimitUpper32; |
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|
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[Description ( |
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"Upper 32 bits of the supported prefetch base address " |
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"when 64-bit addressing is used. The lower 32 bits are " |
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"assumed to be 0." )] |
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uint32 PrefetchBaseUpper32; |
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|
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[Description ( |
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"Upper 16 bits of the supported I/O end address when " |
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"32-bit I/O addressing is used. The lower 16 bits are " |
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"each assumed to be 1." )] |
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uint16 IOLimitUpper16; |
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|
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[Description ( |
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"Upper 16 bits of the supported I/O base address when " |
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"32-bit I/O addressing is used. The lower 16 bits are " |
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"assumed to be 0." )] |
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uint16 IOBaseUpper16; |
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}; |
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